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HEVA/HIVE/H.264 Encoder Video Hardware Accelerator - IP

OverviewFeaturesRequest Datasheet
The Hardware Encoder Video Accelerator (HEVA), supports HEVC encoding low complexity with a
flexible architecture targeting at least 1080p60 with minimal processing units and memory cuts, and
up to 2160p120 with large number of units and large memory cuts.
Trade-off performance/area at design configuration

– Reference cache size for 2160p30 at 350 MHz, 1 reference frame and bandwidth
– overhead of 100% for references i.e. 1.5 GBytes/sec (minimal is 1.2 GB/s)

Hardware interfaces
● Host interface AXI3/AXI4 slave interface for the registers and command/status FIFO
● Memory interface AXI3/AXI4 Streaming interfaces to External DRAM
– Asynchronous AXI3/AXI4 128 bits interface
– Synchronous DMA arbiter and memory interface

Task sequencing modules
– Manages communication and storage between processing modules
– Control the shared memories and caches between the TPU modules and TSU/MIF
– Defines the execution mode of the task processing units

Task processing modules
– Perform the pixel and bit-stream processing under control of TCR/TSU
– The number of processing elements is defined at design configuration to sustain the required
– A local reference cache is needed for performance for some processing units.

Encoder acceleration
– Performance up to 330 Mpixel/sec (2160p30 +1080p30)
– HEVC Main support, Level 4.2 (2160p30)
– H.264 High Profile Progressive, Level 5.1 (2160p30, 1080p120)
– HEVC Sample Adaptive Offset in-loop deblocking
– Full coding unit support (from CU 64x64 to CU 8x8, PU 4x4)
– No restriction on MV range allowed (X<8192, Y<4096)
– Slice support: single slice or number of CTB lines per slice
– Slice level IT programmable

 Original input frame
– Bottom/Right original padding on-the-fly
– YUV 420 semi-planar: NV21
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