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    DDR3/ DDR3L Combo PHY IP

    OverviewFeaturesRequest Datasheet
    The DDR controller is used to control DRAM devices as well as to access the data stored on these devices. Provide multiple AXI interface for AXI master and support DFI 2.1 standard for DDR PHY to support DDR3/3L date rate 800~1600 Mbps, X16, dual rank, Write leveling, Data training, low power mode and  standby mode.
    • Interface: SSTL
    • Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1600Mbps
    • Data path width scales in 8-bit increment
    • Programmable output impedance
    • Programmable input termination (ODT)
    • Core power:1.1V, I/O power(VDDQ):1.5V/1.35V.
    • ESD : 2KV
    • Support ZQ calibration
    • Support Dual-Rank
    • Support DDR3/3L X16
    • Support write-leveling
    • Operation temperature: -40~125C
    • Support Low power mode, Standby mode and Retention mode
    • Four channel AXI and data width 64/128 bits
    • The shape of the DDR PHY is fixed as I type
    Deliverables:
    • User Manual / Application Note
    • Behavior model, and protected RTL codes
    • Protected Post layout netlist and Standard Delay Format (SDF)
    • Synopsys library (LIB)
    • Frame view (LEF)
    • Hspice netlist (SP)
    • Test patterns and Test Documentation

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