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    MIPI RFFE Master Controller IP

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    (English)

    The MIPI RFFE Master Controller IP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The MIPI RFFE Master controller IIP can be implemented in any technology. The Master controller IP core supports the MIPI RFFE 3.0 standard. It can also support a variety of host bus interfaces for easy adoption into any design architecture – AXI, AHB, APB, OCP, VCI, Avalon, PLB, Wishbone or custom buses. The Master IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Master IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.

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    (English)
    • Compliant with version 3.0 MIPI RFFE Specifications.
    • Full MIPI RFFE Master Functionality.
    • Supports following frames
    • ➢ Command Frame
    • ➢ Data/Address Frame
    • ➢ No Response Frame
    • ➢ Bus ownership transfer
    • ➢ Interrupt polling
    • ➢ Master write and read
    • ➢ Master context write and context read
    • Supports extended register read/writes
    • Supports interrupt summary and identification command sequence
    • Supports Master ownership handover
    • Support Master write and read sequence
    • Support Trigger and Extended trigger modes
    • Support Masked write command sequence
    • Support Silent Master initiated bus park
    • Support Synchronous read
    • Support Normal and Secondary operation mode
    • Support USID Programming Procedure 1,2 and 3
    • Supports device enumeration
    • Supports Low power testing Bus-accurate timing
    • Supports half speed
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    • Scan test ready
    • Simple interface allows easy connection to microprocessor/microcontroller devices
    • Optionally this core can be built to have SPI or I2C interface for application where slave can have multiple interfaces like RFFE or SPI or I2C Interface.
    Deliverables
    • RTL design in Verilog
    • Lint, CDC, Synthesis Scripts with waiver files
    • Lint, CDC, Synthesis Reports
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Technical documentation in greater detail
    • Easy to use Verilog Test Environment with Verilog Testcases
    Benefits
    • Fully compliant, silicon-proven core
    • Comes with Verilog test bench and option to buy full advanced System Verilog Test bench
    • Support directly from engineer who designed the code.
    • Based on RMM (Re Use Methodology Manual guidelines)
    • Supports all the Synthesis tools

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