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    PCIe 3.0 Controller IP

    OverviewFeaturesRequest Datasheet

    PCIe Gen3 Controller is a configurable and scalable for ASIC and FPGA implementation. The Controller P is compliant with the PCI Express 4.0, and 3.1/3.0 specifications, as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification. The IP can be configured to support endpoint, root port, and dual-mode topologies, allowing for a variety of use models, and exposes a configurable, flexible AMBA AXI interconnect interface to the user.

    The PCIE Controller IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The PCIE Controller IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.

     

    Related Links : Design & Reuse | ChipEstimate | Anysilicon 

    • Compliant with PCIE 1.0/2.0/3.0/4.0/5.0 Specifications
    • Full PCIE Controller functionality
    • Supports PIPE interface.
    • Compatible with Gen1,2,3,4 and 5
    • Supports following BFM modes
    • o Root Complex
    • o Endpoint
    • Supports queuing for 8 Virtual Channels with configurable depth Supports up to 8 Traffic Classes
    • Supports multi-function Configurable TC to VC queue mapping
    • Supports full link speed and width negotiation up to 8 Lanes
    Benefits
    • Fully compliant, silicon-proven core
    • Comes with Verilog test bench and option to buy full advanced System Verilog Test bench
    • Support directly from engineer who designed the code.
    • Based on RMM (Re Use Methodology Manual guidelines)
    • Supports all the Synthesis tools.
    Applications
    • PC
    • Digital TV
    • Set-top boxes
    • Enterprise computing, storage area networks, networking switches, and routers
    • Wireless and mobile devices
    • Industrial, automotive, and IoT
    • Embedded systems
    • Graphics devices
    • Laptops
    • Workstations
    • Servers
    Deliverables
    • RTL design in verilog
    • Technical documentation in greater detail
    • Easy to use Verilog Test Environment with Verilog Test cases.
    • Digital Digital Digital lP controller with UVM VIP counterpart and relatable testbench components and all documentations
    • Hardware validation platforms with full compliance testing support and error scenario support
    • Bit file for digital IP controllers for any type of platforms

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