Select Language

Your Complex IP Core Partner

    SPI Master / Slave Controller IP

    OverviewFeaturesRequest Datasheet
    (English)

    The SPI IP is a revolutionary octal SPI designed to offer the fastest operations available for any serial SPI memory. It is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Moreover, the IP Core supports all 8, 16, 32 bit processors available on the market. The SPI IP is a fully configurable SPI master/slave device, which allows you to configure polarity and phase of serial clock signal SCK. It enables the microcontroller to communicate with fast serial SPI memories and serial peripheral devices. Moreover, it’s capable of inter processor communications in a multi‐master system. A serial clock line (SCK) synchronizes shifting and sampling of information on four serial data lines. In the Single SPI mode, data is simultaneously transmitted and received, while in DUAL, QUAD and OCTAL SPI modes, data is shifted in or out respectively on two, four and eight data lines at once. Additionally, transfer speed can be doubled by using the DDR protocol (Double Data Rate) – this feature allows the SPI to transfer / receive data on both falling and rising edges of SCK. The DDR together with OCTAL SPI transfer allow 8 bits of data to be sent / received within a single SCK clock cycle. This makes the SPI perfect for systems, where performance is essential, or where the code can be moved from non-volatile memory to fast RAM, or for systems where device size and cost are the key, or where the program code can be executed directly from non-volatile memory, using an approach known as Execute-in-Place.

    The SPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or slave device. Data rates as high as CLK/2, when other vendors’ solutions offer just CLK/8. Clock control logic allows selecting clock polarity, phase and four fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects bit rates for the serial clock. The SPI automatically drives selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O), and addresses SPI slave device to exchange serially shifted data. Error‐detection logic is included, to support inter processor communications. A write‐collision detector indicates when an attempt is made to write data to the serial shift register, while the transfer is in progress. A multiple-master mode‐fault detector disables SPI output drivers automatically, if more than one SPI device simultaneously attempts to become a bus master. The SPI supports two DMA modes: single transfer and multi‐transfer. These modes allow the SPI to interface to higher performance DMA units which can interleave their transfers between CPU cycles or execute multiple byte transfers. The SPI is fully customizable – it is delivered in the exact configuration to meet your requirements.

       
    t2m-design-reuse t2m-chipestimate t2m-anysilicon
       
    (English)
    • Operates with 8, 16 and 32 bit CPUs
    • Full duplex synchronous serial data transfer
    • DMA support
    • Support for 32, 16 and 8 bit systems
    • Support for various system Bus Standards
    • Single, Dual, Quad and Octal SPI transfer
    • DDR support (Double Data Rate)
    • Multi master system supported
    • Optional FIFO size extension (128, 256, 512B)
    • Up to 7 SPI slaves can be addressed (more Slave Select Outputs can be added upon request)
    • Software Slave Select Output – SSO ‐ selection
    • Automatic Slave Select outputs assertion during each byte transfer
    • System error detection
    • Interrupt generation
    • Various Bit rates supported
    • Bit rate in fast SPI Mode ½ CLK
    • Four transfer formats
    • Simple SPU and DMA interface
    • Fully synthesizable, static synchronous de-sign with no internal tri‐states
    Deliverables
    • Source code:
    • VHDL Source Code or/and
    • VERILOG Source Code or/and
    • Encrypted, or plain text EDIF
    • VHDL & VERILOG test bench environment
    • Active-HDL automatic simulation macros
    • Model Sim automatic simulation macros
    • Tests with reference responses
    • Technical documentation
    • Installation notes
    • HDL core specification
    • Datasheet
    • Synthesis scripts
    • Example application
    • Technical support
    • IP Core implementation support
    • 3 months maintenance
    • Delivery of the IP Core and documentation updates, minor and
    • major versions changes
    • Phone & email support
    Applications
    • Embedded microprocessor boards
    • Consumer and professional audio/video
    • Home and automotive radio
    • Low-power applications
    • Communication systems
    • Digital multimeter

      Fill the form below, to receive the product datasheet in your inbox