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    DVB S2X Satellite Full Band Capture Tuner Demodulator SoC White Box IP

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    Description

    The iD135 has been designed for Satellite Broadband applications, leveraging Ka-band and multi-spot beam technology carried by the latest high-throughput satellites (HTSs).

    The iD135 has been designed to enable single-carrier usage of HTS transponders. The device implements two high-symbol-rate (HSR) demodulators compliant with Annex M of the DVB-S2/S2X specification EN 302 307, and provides full HW support for network clock recovery (NCR) in order to enable external return-channel modulators.

    The iD135 may be used in standard broadcast environments as an 8-channel DVB-S2/S2X receiver enabling multi-channel distribution and/or fast channel change scenarios.

    Features

      Two high-symbol-rate (HSR) demodulators:
    • Maximum baud rate 500 Msymbol/s
    • Up to two slices each
    • DVB-S2/S2X and Annex M compliant
    • Up to 8 multi-standard demodulators:
    • S/S2/S2X/DTV
    • Integrated full-band tuners and ADCs
    • High-speed digital multiplexer to connect any tuner to any demodulator
    • NCR PLL support
    Flexible transport stream processor:
    • PID filtering, PCR re-stamping and re-labelling, GSE label filtering
    • TS merger (multiplex)
    • Channel bonding
    • Low power consumption
    • Wake-on-network PID or GSE label
    • Fast auto scan
    • Signal monitoring, spectral analysis, bit error rate test and reporting
    Interfaces:
    • Crystal oscillator
    • I2C serial bus interface, including private repeater for optional LNA
    • TS, 8 serial, 2 parallel or multiplexed
    • JTAG for boundary scan
    • DiSEqC 1.x and DiSEqC2.x compatible receiver, 22-kHz
    • FSK modem
    • Flexible GPIOs and interrupts
    Technology:
    • Single rail supply with inbuilt SMPSs for internal supply generation
    • Fine-grained power management
    • VQFPN-mr 13x13 mm2 package, RoHS
    • Temperature range -40 to +85 °C ambient

    Applications

    • Verilog Source RTL Code plus Simulation Environment
    • Technical Documents

    Deliverables

    • Verilog Source RTL Code plus Simulation Environment
    • C Source Code
    • Physical Design scripts - Synopsys synthesis
    • Hardware simulation test bench with regression test suit
    • Reference platform drivers

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