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    DVB-T2/T Modulator IP

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    This DVB-T2/T Modulator IP core provides all the necessary processing steps to modulate single transport stream into a complex I/Q signal for input to a pair of DACs, or interpolating DAC devices such as the AD9857/AD9957 or RFDACs such as the AD9789. Optionally the output can be selected as an IF to supply a single DAC. Additional extension cores are available for multiple PLP (common/data) support, T2MI interface support and SFN deployment support. The design has been optimised to provide excellent performance in low cost FPGA devices such as the Cyclone range from Altera or the Spartan range from Xilinx.

    A description of the processing steps follows: TS Processing. The TS processing block performs rate adaptation functions in Broadcast applications to ensure that variable transmission delays do not result in disturbances of time-critical services such as audio and video. Both normal-mode and HighEfficiency-Mode(HEM) processing is supported. Null packet deletion. The Null packet deletion block removes null TS packets from the input stream to maximise the capacity available for information services in VCM and ACM modes. The mechanism defined by DVB-T2 allows for complete restoration of the input stream where null packets are necessary to maintain a constant delay. CRC-8 Encoding. An 8-bit CRC is added to each outgoing TS packet and serves to allow packet-level error detection at the receiver. Baseband buffer and Padding. The baseband padding block inserts a fixed-length Baseband Header at the start of each BBFRAME and pads to the end of the frame during ACM operation. The structure of the Baseband Header is as described in EN 302 755. Baseband Scrambling. The baseband scrambler block performs the energy dispersal and transport multiplex adaptation using the DVB randomization polynomial 1+x14+x15. When processing L1-field frames (L1PRE/L1POST), zero padding is added to ensure the non-standard L1 frame length is compliant prior to FEC encoding. BCH, LDPC Encoders. These blocks systematically encode each frame and append error correction information bits. When processing L1-field frames (L1PRE/L1POST), puncturing is performed where necessary following FEC encoding. Bit Interleaver and Demux. The bit interleaver block applies block-based and column-twist bit interleaving to the coded frame prior to symbol demultiplexing and mapping.

    Mapping and Rotation. This block performs the QAM constellation mapping using the mapping schemes specified by DVB for BPSK, QPSK, QAM16, QAM64 and QAM256. Optionally constellation rotation is applied as indicated by the L1FIELD information fields, together with L1-ACE modifications when enabledMore detailed info on request, under NDA.


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    • Fully compliant with ETSI EN 300 744 V1.5.1. Extension core available for DVB-T2/T(H) support.
    • Enables rapid development of audio/visual systems using commodity Free-to-Air set-top-box technology and low-cost FPGAs.
    • Configurable support for 2K and 8K OFDM modes and hierarchical transmission. (4k for DVB-T(H)).
    • Variable channel bandwidth support using a single.
    • clock reference; 5MHz… 8MHz.
    • AD9857/AD9957/AD9789 interface and auto- programming support.
    • AD9516/ADF4350 PLL programming support.
    • Optional dual-core combining into the AD9857 for multi-channel applications.
    • Extension core available for SPI/ASI interface with integrated PCR TS re-stamping, NULL TS packet removal/filtering, NULL/PRBS TS packet insertion, input and output TS rate estimation registers.
    • Seamless integration with Altera ASI megacore when using SPI/ASI extension core.
    • Optional FFT output windowing. Optional critical-mask output filtering.
    • Optional in-band or output pre-distortion. Optional noise interference source.
    • Modes that are not required may be removed with synthesis options to generate a compact, efficient design.
    • Designed for very efficient FPGA implementation without compromise to the targeting of gate array or standard cell structures.
    • Supplied as a protected bitstream or netlist (Megacore for Altera FPGA targets).
    • Fully Packaged
    • Ready to license
    • Tested and complete Netlist design
    • Pre and post-sales support
    • Digital TV
    • STB
    • Satellite ground and space
    • Defense projects
    • Complete Netlist code package
    • Verification test, test benches
    • Complete datasheets sets

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