This is a member of the high-speed Memory Interface family. This combo PHY is suitable to work with DFI 3.1 compliant memory controller and JEDEC DRAM memories. The state-of-art DDR PHY provides a comprehensive feature set, a well-defined architecture that allows designers extensive flexibility for various applications, and a roadmap to future products. The benefits of our highly integrated PHY solutions include straight forward integration, differentiated performance, simplified interoperability, and extensive built-in testability.
This minimizes risk with extensive pre -silicon verification/interoperability program, resulting in highly reliable products, which are manufacturable in leading CMOS processes.Our enterprise class PHY offers up to 4 chip-select with independent training on each of them. PHY handles all the complex timing relationship and electrical specification required for successful DRAM operation.
Synthesizable RTL along with superior analog DLL and propriety implementation flow enables meeting all the critical timing requirements with relative ease. This PHY allows simple SoC integration by using DFI interface alone and requiring fewer programming