PCI Gen4.0 16Gbps PHY – Description

Description

  • T2M offers best in class highly configurable 16Gbps SerDes PHY, targeted for both enterprise and client application, complaint to PCie 4.0 specification 0.3. The PHY IP is designed to support a wide range of applications and can provides maximum throughput. The customer has a choice to customize it for lower data rates and upto 4 lanes configuration. This SerDes PHY integrated with partner company PCIe 4.0 controller to offer an complete integrated PCIe 4.0 hard IP.
  • This SerDes supports wide range of industry Standards including PCIe 4.0, USB 3.1, XFI/SFI, JESD204B etc.
  • PCIe_GEN4.0_PHY is multi-standard, high performance, low power, Single-Lane PCI Express Electrical PHY that can handle high level PCI Express protocol and its signalling needs. It is compliant to PCI Express Gen 4.0 base specifications 0.3 by PCI-SIG team and has features like clocking and clock & Data recovering, Serialization and De-Sterilization of Data, 128/130b 8/10b, data coding, Receiver detection and support high performance to Media Access Control layer device.
  • T2M’s PCIe GEN 4.0 PHY uses 32/16bit Data PIPE interface. Its PIPE interface is a super set of PIPE interface for the PCI Express (PIPE) 4.0 specifications. It also supports latest lower power management’s states like L0s, L1, L1-sub-states and L2. PHY Gen 4.0 PHY IP is available in TSMC 28nm HPC/HPC+ process .
  • Available SerDes PHY for the 10G/5G/2.5/10/16 Gbps
  • Foundry 28,55 and 65nm