This USB 3.2 Dual Mode Controller IP can be configured to support host, device functionality. It provides a standard USB3.1 PIPE(v4.3) interface enabling easy integration with third party or customers PHY. This controller has a very simple application interface, which can be easily adapted to standard on-chip-bus interfaces such as AHB, AXI, OCP etc as well as standard off-chip interconnects. Its flexible backend interface makes it easy to be integrated into wide range of applications. The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools, and most importantly, the target technology. Our solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally.
This core can operate either in Host mode or Device mode based on a Mode select input strap pin. For USB 3.2 mode of operation, MAC, Link layer is shared between Host mode and Device mode. Dedicated Protocol Layers are used for Host and Device Mode of operation. The core utilizes separate USB 2.0 Transaction controller for Host and Device Mode of operation. The core exposes either a UTMI (typically when integrating a third party USB 2.0 PHY) or a ULPI interface (typically when interfacing to an external discrete USB 2.0 PHY chip). For USB 3.2 it’s a 32-bit PIPE interface. The core supports a 64-bit AXI Master Interface. Slave register access interface is 32-bit AHB.
Adaptable RTL Implementation
HDL-based Test Environment with Behavioral Models
Test Scenarios and Suites
Protocol Compliance Checkers, Bus Monitors, and Performance Analyzers
Configurable Synthesis Framework
Design Guidelines
Verification Handbook
Synthesis Protocol Guide
FPGA Validation Platform for Pre-Tape-out Testing
Firmware Reference Implementation
