SDR Gen1 RF IP (300MHz~2.8GHz)
This is the 1st Generation Software Defined Radio (SDR) RF IP that supports 1x2 and support the frequency ranging from 300MHz to 2.8 GHz with a support of up to 40MHz Bandwidth. the SDR Gen.1 supports the ADC/DAC with 160/640Msps sampling speed.
This Software Defined Radio (SDR) RF IP family are ultra-low-power radio solutions optimized from IoT and M2M to 5G applications. They integrate all the necessary RF/analog/mixed-signal functions to support radio functions for most standards operating in this frequency range at low-cost and ultra-low-power.
The receive path (RX) has very high dynamic range and is implemented with direct-conversion architecture without external SAW filter. A direct conversion TX generates low EVM signals to drive the external power amplifier. An integrated Frac-N frequency synthesizers and LO-chains generate the required low phase-noise LO signals for TX and RX mixers. Optional fully integrated power management can be integrated to minimize the module eBOM cost.
This unique SDR RF IP family support many wireless market standards, including: 5G, Wi-Fi, LTE, NB-IoT, 802.15.4g, 802.11ah, Bluetooth, LORA, GNSS/GPS among others. This ultra-low-power transceiver IP enables Internet-of-Things (IoT) and Machine-to-Machine (M2M) applications.
The other generation of the Software Defined Radio (SDR) RF IP are as follows:
● SDR2: TSMC65, 2x2, 100MHz-3.8GHz, up to 120MHz bandwidth, 160/640 MSPS ADC/DAC, FD-FDD
● SDR3: TSMC40, 1x1 100MHz ̴ 2.6GHz, up to 80MSPS ADC/DAC, TDD/HD-FDD, optimized for IoT
● SDR4: TSMC22, 200MHz ̴7.3GHz, (2022 sampling), TDD/FD-FDD
- Frequency Range: 300MHz~2.8GHz
- Supports HD-FDD/TDD modes.
- Low phase-noise Frac-N synthesizer
- Fast PLL for frequency hopping
- Modulation Support: OFDM, QPSK, QAM, OQPSK
- Transmit power: +23 dBm
- Integrated DPD to improve Tx power efficiency and linearity.
- ADC/DAC: 10/12bit SAR 80/160 Msps
- Integrated LDOs and DC-DC
- Low Rx. Power: ~ 10mW (w/o LDO mode)
- Silicon : TSMC 65ULP
- Power Supply Voltage: VDDH=3.3V
- VDDL=0.95V (1.2V if internal LDOs are used.)