DVB-S2X Narrowband Demodulator and Decoder IP
This is NarrowBand demodulator IP is silicon proven and extratced from production chipsets, it performs demodulation according to DVB-S, legacy DirectTV, DVB-S2 and DVB-S2X specifications. The input signal from the tuner is A-to-D converted on 10 bits. The DC offset, amplitude mismatch and quadrature error are corrected and the AGC signal level to the tuner is calculated. The carrier frequency offset is corrected. Then the signal is sub sampled and Nyquist root filtered. The signal amplitude is controlled through the second stage (AGC2) block. The pilots, when present, are used to help phase lock to the symbol stream. The signal is equalized, descrambled, and passed to the FEC. An internal state machine controls the automatic acquisition of a channel with various entry points, including warm start (known symbol frequency, small carrier offset), cold start (known symbol frequency and large carrier frequency offset), and blind search (all parameters unknown).
The DVB S2X NarrowBand IP main demodulation path takes its data from a dual ADC sampling the signals I/Q coming from an external tuner. The ADC is clocked at 135MHz and the data are on 10bits. After demodulation, the data is sent either to a DVB-S Forward Error Correction (FEC) path or a DVB-S2 FEC path.
The DVB-S FEC is based on a Viterbi and Reed-Solomon decoders. A SuperFEC mode is also implemented where a second Viterbi block is added to improve the performances. The DVB-S2 FEC is based on a LDPC+BCH decoder and a packet delineator block needed to extract the physical packets (MPEG or GSE) from the FEC frame. The decoded & corrected data is then sent to a transport stream interface managing standard TS-based transmission to the back-end decoder. In addition to this main demodulation path, peripheral interfaces are integrated, a DiSEqC and an FSK interfaces.They are both protocols to communicate with the LNB antenna on the coaxial cable.
- Two high-symbol-rate (HSR) demodulators: – Maximum baud rate 500 Msymbol/s, Up to two slices each, DVB-S2/S2X and Annex M compliant
- Up to 8 multi-standard demodulators:– S/S2/S2X/DTV
- Integrated full-band tuners and ADCs
- High-speed digital multiplexer to connect any tuner to any demodulator
- NCR PLL support
- Flexible transport stream processor: PID filtering, PCR re-stamping and re-labelling, GSE label filtering
- Low power consumption
- Wake-on-network PID or GSE label
- Fast auto scan
- Signal monitoring, spectral analysis, bit error rate test and reporting
- Interfaces: – Crystal oscillator, I2C serial bus interface, including private repeater for optional LNA, TS, 8 serial, 2 parallel or multiplexed, JTAG for boundary scan, DiSEqC 1.x and DiSEqC2.x compatible receiver, 22-kHz, FSK modem, Flexible GPIOs and interrupts
- Verilog Source RTL Code plus Simulation Environment
- RTL/C Source Code
- Physical Design scripts - Synopsys synthesis
- Hardware simulation test bench with regression test suit
- Reference platform drivers
- Complete Design Database