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DVB-S2X Wideband Demodulator and Decoder IP

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This is a high-performance, dual high-symbol-rate (HSR) DVB-S2/S2X demodulator IP extarcted from production chipsets with integrated tuner and silcon proven technology. The demodulators are compliant with Annex M of the DVB-S2 specification EN 302 307 and can demodulate signals up to 500 Msymbol/s. Each HSR demodulator may demodulate up to 2 slices. This implements 8 multi-standard demodulators capable of DVB-S, DTV legacy, DVB-S2 and DVB-S2X broadcast-profile signal processing.

This IP incorporates a high-speed DVB-S2 forward error corrector (FEC) which is designed to handle up to 720 Mchannel-b/s at its input. This allows for 8 simultaneous 8PSK decodes at 30 Msymbol/s. This capacity is shared between the demodulators and may be allocated at will, provided that the maximum capacity limit is not exceeded.This IP features four integrated full-band capture tuners which cover the band 950 to 2150 MHz. The signal is sampled by high-performance analog to digital converters with built in anti-aliasing filters.These ADCs connect to a high-speed digital multiplexer which allows any tuner input to feed any of the 8 demodulators.

This implements full S2 and S2X interactive services capability with short frames and full-ACM functionality including MODCOD blocking. An NCR PLL compatible with both MPEG2 and GSE streams has been implemented and may be associated with any of the demodulators to assure return-channel synchronization. A transport stream processor is able to filter on PIDs, carry out PCR re-stamping and conduct PID relabeling. In this way the wanted program streams can be, for example, output on a single multiplexed bus thus reducing wiring complexity and saving board space. The transport stream processor is also capable of handling GSE, GSE-lite, IP streams and can output raw, baseband fames.

This integrates all the features needed to provide a low-cost multi channel broadcast satellite receiver solution including: integrated crystal oscillator, SMPSs for single wire supply, DiSEqC controller, I2C repeater, FSK modem, ancillary DACs and ADCs and many unattributed general-purpose input-output ports for peripheral control. Advanced power-saving features have been implemented, the LDPC stops once the solution is sufficiently converged and the various blocks of the IC (tuner, demodulator, LDPC, Legacy FEC, and so on) may be completely shut down if not required. The device also supports Wake-on-network PID.

  • Two high-symbol-rate (HSR) demodulators: – Maximum baud rate 500 Msymbol/s, Up to two slices each, DVB-S2/S2X and Annex M compliant
  • Up to 8 multi-standard demodulators:– S/S2/S2X/DTV
  • Integrated full-band tuners and ADCs
  • High-speed digital multiplexer to connect any tuner to any demodulator
  • NCR PLL support
  • Flexible transport stream processor: PID filtering, PCR re-stamping and re-labelling, GSE label filtering
  • Low power consumption
  • Wake-on-network PID or GSE label
  • Fast auto scan
  • Signal monitoring, spectral analysis, bit error rate test and reporting
  • Interfaces: – Crystal oscillator, I2C serial bus interface, including private repeater for optional LNA, TS, 8 serial, 2 parallel or multiplexed, JTAG for boundary scan, DiSEqC 1.x and DiSEqC2.x compatible receiver, 22-kHz, FSK modem, Flexible GPIOs and interrupts
  • Verilog Source RTL Code plus Simulation Environment
  • RTL/C Source Code
  • Physical Design scripts - Synopsys synthesis
  • Hardware simulation test bench with regression test suit
  • Reference platform drivers
  • Complete Design Database
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