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DVB-S2X Decoder IP

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The DVB-S2/S LDPC/BCH decoder a silicon proven IP extracted from production chips has an octal input interface and a single output interface. The data coming from the 8 demodulators are multiplexed and decoded by the same engine. After decoding, 8 packet delineators do the demultiplexing and DVB-S2 de-framing before sending data to the output transport stream manager. For a 258-MHz clock we may have a maximum data rate of 258 Mchannel-bit/s (megaLLRs)at the input to the FEC decoder. Advanced power-saving features have been implemented, the LDPC stops once the solution is sufficiently converged and the various blocks of the IC (tuner, demodulator, LDPC, Legacy FEC, and so on) may be completely shut down if not required. The device also supports Wake-on-network PID.
   
  • Two high-symbol-rate (HSR) demodulators: – Maximum baud rate 500 Msymbol/s, Up to two slices each, DVB-S2/S2X and Annex M compliant
  • Up to 8 multi-standard demodulators:– S/S2/S2X/DTV
  • Integrated full-band tuners and ADCs
  • High-speed digital multiplexer to connect any tuner to any demodulator
  • NCR PLL support
  • Flexible transport stream processor: PID filtering, PCR re-stamping and re-labelling, GSE label filtering
  • Low power consumption
  • Wake-on-network PID or GSE label
  • Fast auto scan
  • Signal monitoring, spectral analysis, bit error rate test and reporting
  • Interfaces: – Crystal oscillator, I2C serial bus interface, including private repeater for optional LNA, TS, 8 serial, 2 parallel or multiplexed, JTAG for boundary scan, DiSEqC 1.x and DiSEqC2.x compatible receiver, 22-kHz, FSK modem, Flexible GPIOs and interrupts
Deliverables
  • Verilog Source RTL Code plus Simulation Environment
  • RTL/C Source Code
  • Physical Design scripts - Synopsys synthesis
  • Hardware simulation test bench with regression test suit
  • Reference platform drivers
  • Complete Design Database
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