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T2M › › DDR3 Controller IP

DDR3 Controller IP

Description and Features

DDR3 interface provides full support for the DDR3 interface, compatible with JESD79-3F specification and DFI-version 2.0 or higher Specification Compliant. Through its DDR3 compatibility, it provides a simple interface to a wide range of low-cost devices. DDR3 IP is proven in FPGA environment. The host interface of the DDR3 can be simple interface or can be AMBAAHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.

Features
  • Supports DDR3 protocol standard JESD79-3F Specification.
  • Compliant with DFI-version 2.0 or higher Specification.
  • Supports all the DDR3 commands as per the specs.
  • Supports up to 16 AXI ports with data width upto 512 bits.
  • Supports controllable outstanding transactions for AXI write and read channels
  • Supports in port arbitration and multi-port arbitration.
  • Supports user programmable page policy. • Closed page policy • Open page policy
  • Supports Error Checking and correction (ECC).
  • Supports retry on ECC error, with retry limit user controllable.
  • Supports high clock speeds in ASIC and FPGA.
  • Supports low latency for write and read path.
  • Supports reordering of transactions for higher performance.
  • Supports 512MB, 1GB, 2GB, 4GB, 8GB densities.
  • Supports 8 internal banks.
  • Supports X4, X8, X16 devices.
  • Supports all speed grades as per specification.
  • Quickly validates the implementation of the DDR3 standard JESD79-3F.
  • Supports Programmable Write latency and Read latency.
  • Supports On-the-fly for burst length.
  • Supports Programmable burst lengths: 4,8.
  • Supports the following burst order. • Sequential • Interleave
  • Supports for All Mode registers programming.
  • Supports for Write data Mask.
  • Supports for Power Down features.
  • Supports for input clock stop and frequency change.
  • Supports for DLL.
  • Supports for Write levelling.
  • Supports for ZQ Calibration.
  • Supports for automatic self-refresh.
  • Supports for ODT (On-Die Termination).
  • Build in self-test to test all locations in memory to identify damaged locations.

Benefits

  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

  • The DDR3 interface is available in Source and netlist products.
  • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.
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