DDR5 is full-featured, easy-to-use, synthesizable design, compatible with DDR5 JESD79-5 and JESD79-5 Rev1.40 (Draft) specification and DFI-version 5.0 Compliant. Through its DDR5 compatibility, it provides a simple interface to a wide range of low-cost devices. DDR5 IP is proven in FPGA environment. The host interface of the DDR5 can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.
Supports DDR5 protocol standard JESD79-5 Specification.
Compliant with DFI version 5.0 Specification.
Supports up to 16 AXI ports with data width upto 512 bits.
Supports controllable outstanding transactions for AXI write and read channels
Supports in port arbitration and multi-port arbitration.
Supports user programmable page policy.
o Closed page policy
o Open page policy
Supports Error Checking and correction (ECC).
Supports retry on ECC error, with retry limit user controllable.
Supports high clock speeds in ASIC and FPGA.
Supports low latency for write and read path.
Supports reordering of transactions for higher performance.
Supports up to 64GB device density.
Supports X4, X8, X16 device types
Supports all speed grades as per specification.
Supports for Mode Registers programming.
Supports for Sequential burst type.
Supports Programmable burst lengths of 8,16 & 32.
Supports for Programmable Write and Read latency.
Supports Multiple Outstanding transaction.
Supports In-port Arbitration using QoS.
Supports Write Pattern Comand.
Supports Auto precharge for Write, Read and Write pattern command.
Supports for Write Data Mask.
Supports Refresh modes and Global refresh counter.
Supports Refresh management all command.
Supports Refresh management same bank command.
Supports 2N mode.
Supports CRC and ECC for Write and Read Operations.
Supports for Self-Refresh and Power Down operation.
Supports for Precharge Command modes.
Supports for Maximum Power Saving Mode (MPSM).
Supports 1:4 and 1:2 Controller to DFI PHY frequency ratio.
Supports Programmable clock frequency operation.
Deliverables
The DDR5 interface is available in Source and netlist products.
The Source product is delivered in Verilog. If needed VHDL, SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases
Lint, CDC, Synthesis, Simulation Scripts with waiver files
IP-XACT RDL generated address map
Firmware code and Linux driver package
Documentation contains User's Guide and Release notes.
