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Ethernet 100G PCS IP

Description and Features

Ethernet 100G PCS core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 100G PCS IP is proven in FPGA environment. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

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Features
  • Supports IEEE Standard 802.3.2018 Clause 82
  • Supports 100G BASE R, BASE KR4/CR4
  • Supports 64b/66b encoding and decoding for transmit and receive path
  • Supports data scrambling on the transmit path and descrambling on the receive path
  • Supports Lane Distribution across 20 Lanes for 100Gbps BASE R and 4 lanes for BASE KR4/CR4
  • Supports Block synchronization
  • Supports gearbox for various data widths
  • Supports Alignment Marker insertion and removal
  • Supports PCS Lane Deskew and Lane Re-ordering
  • Supports BIP-8 insertion on the transmit path and checking on the receive path per lane
  • Supports Bit Error Rate monitoring
  • Supports receiver Link fault status detection
  • Supports Loopback functionality
  • Supports IEEE 802.3az Energy Efficient Ethernet
  • Supports Configurable Management Interface (MDIO (Clause 45) / SOC Bus)
  • Supports PMA interface for the following widths, • 32 • 40
  • Support RS FEC as per clause 91 of IEEE Standard 802.3.2018
  • Optional Support for Base-R FEC as per clause 74 of IEEE Standard 802.3.2018
  • Optional support for Test pattern generation and error checkers
  • Optional support for auto negotiation for backplane Ethernet as per clause 73 of IEEE Standard 802.3.2018
  • Programmable PRBS31 and PRBS9 test pattern generation and checker
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices

Deliverables

  • Verilog RTL design

  • Integrating waivers seamlessly into validation scripts for comprehensive coverage of Linting, CDC analysis, and Synthesis

  • Providing detailed and comprehensive reports offering extensive insights into Linting, CDC analysis, and Synthesis methodologies

  • Efficiently leveraging IP-XACT RDL to produce address maps

  • Consolidating firmware code and Linux drivers into a unified package

  • Offering exhaustive technical documentation covering all components and aspects thoroughly

  • Establishing a Verilog Test Environment with intuitive integration of cohesive test cases for thorough testing

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