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    DDR Controller IP

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    DDR interface provides full support for the DDR interface, compatible with JESD79F specification and DFI-version 2.0 or higher Specification Compliant. Through its DDR compatibility, it provides a simple interface to a wide range of low-cost devices. DDR IP is proven in FPGA environment. The host interface of the DDR can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXILite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.

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    • DDR protocol standard JESD79F Specification.
    • Compliant with DFI-version 2.0 or higher Specification.
    • Supports all the DDR commands as per the specs.
    • Supports up to 16 AXI ports with data width upto 512 bits.
    • Supports controllable outstanding transactions for AXI write and read channels
    • Supports in port arbitration and multi port arbitration.
    • Supports user programmable page policy. • Closed page policy • Open page policy
    • Supports Error Checking and correction (ECC).
    • Supports retry on ECC error, with retry limit user controllable.
    • Supports high clock speeds in ASIC and FPGA.
    • Supports low latency for write and read path.
    • Supports reordering of transactions for higher performance.
    • Supports all device speeds as per specification.
    • Supports Programmable CAS latency.
    • Supports Programmable burst lengths: 2,4 and 8.
    • Supports Write data Mask.
    • Supports the X4, X8, X16 devices.
    • Supports the 64MB, 128MB, 256MB, 512MB, 1GB memory densities.
    • Supports the following burst types. • Sequential • Interleave
    • Supports burst order.
    • Supports for All Mode registers programming.
    • Supports for Extended Mode registers programming.
    • Supports Auto refresh & self refresh modes.
    • Supports Auto precharge option for each burst access.
    • Supports Power Down features.
    • Supports input clock stop and frequency change.
    • Supports DLL operation.
    • Fully synthesizable
    • Static synchronous design.
    • Positive edge clocking and no internal tri-states.
    • Scan test ready
    • Simple interface allows easy connection to microprocessor/microcontroller devices
    • Single site license option is provided to companies designing in a single site.
    • Multi sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The DDR interface is available in Source and netlist products.
    • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Documentation contains User's Guide and Release notes.

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