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    LPDDR3 Controller IP

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    LPDDR3 interface provides full support for the LPDDR3 interface, compatible with JESD209-3, JESD209-3B and JESD209-3C specification and DFIversion 3.1 or higher specification Compliant. Through its LPDDR3 compatibility, it provides a simple interface to a wide range of low-cost devices. LPDDR3 Controller IP is proven in FPGA environment. The host interface of the LPDDR3 can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.

    Related Links: Design & Reuse | ChipEstimate | Anysilicon
    • Supports 100% of LPDDR3 protocol standard JESD209-3, JESD209-3B and JESD209-3C.
    • Compliant with DFI version 3.1 or higher Specification.
    • Supports all the LPDDR3 commands as per the specs.
    • Supports up to 16 AXI ports with data width upto 512 bits.
    • Supports controllable outstanding transactions for AXI write and read channels
    • Supports in port arbitration and multi-port arbitration.
    • Supports user programmable page policy. • Closed page policy • Open page policy
    • Supports Error Checking and correction (ECC).
    • Supports retry on ECC error, with retry limit user controllable.
    • Supports high clock speeds in ASIC and FPGA.
    • Supports low latency for write and read path.
    • Supports reordering of transactions for higher performance.
    • Supports up to 32GB device density
    • Supports X16 and X32 devices.
    • Supports all data rates as per specification.
    • Supports for Programmable READ/WRITE Latency timings.
    • Supports for Burst sequence.
    • Supports for All Mode register programming.
    • Supports for write data mask and data strobe features.
    • Supports for Power Down features.
    • Supports for Deep Power Down features.
    • Supports for Write leveling.
    • Supports for ZQ calibration.
    • Supports for CA training and DQ calibration.
    • Supports for ODT (On-Die Termination features).
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    • Scan test ready
    • Simple interface allows easy connection to Microprocessor/Microcontroller devices.
    • Single site license option is provided to companies designing in a single site.
    • Multi sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The LPDDR3 interface is available in Source and netlist products.
    • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Documentation contains User's Guide and Release notes.

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