Our Display Port is VESA DP1.1a, DP1.2 and eDP compliant with four main lanes and an auxiliary channel The DP transmitter acceptsDP1.1a HBR (2.7Gbps) and RBR (1.62Gbps) data rates; it can also support turbo mode (3.24Gbps) and HBRII (5.4Gbps) of DP1.2 standard. Signals are sampled from 1/2/4-lane double-wide DP stream data.

• Display Port v1.2 Transmitter [1.62 - 2.7 - 5.4 Gbps/lane]
• Embedded Display Port v1.4 Transmitter
• HDMI v1.4 and Display Port v1.2 Combo receiver
• DP SST and MST compliant
• Support video format of RGB, YCbCr 4:4:4/4:2:2
• Deep color up to 16bit per component, H Sync, V Sync, Field ID (Interlaced modes) and DE.
• Support dual bus video
• Audio up to 4ch I2S
• Support HDCP 1.3
• VESA DP1.1a, DP1.2a, eDP v1.3 and iDP v1.0 compliant
• DP1.1a HBR (2.7Gbps), RBR (1.62Gbps) Turbo mode (3.24Gbps) and HBRII (5.4Gbps)
• Support DP 1.2 side band and GTC messages
• Support DP 1.2 3D and SDP nesting
• To facilitate lower test cost and improve test coverage, a loopback test is provided to check for the functionality of the transmitter in different speed modes

• Verilog RTL or netlist source code of LINK controller.
• Abstracted timing models for synthesis and STA
• Timing constrains for synthesis and physical layout
• Behavioural Verilog Model, simulation test bench, run control scripts, and test stimuli
• Physical design database
• Integration guidelines
• Reference software sample code