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    Ethernet 10G TSN MAC IP

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    The Ethernet 10G TSN MAC IP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The Ethernet 10G TSN MAC IP can be implemented in any technology. The Ethernet 10G TSN MAC IP core supports the Various Ethernet TSN IEEE standards. It integrates hardware stacks for timing synchronization (IEEE Standard 802.1AS) and traffic shaping (IEEE Standard 802.1Qav and 802.1Qbv), and a low-latency Ethernet MAC. It supports Preemption. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses . The Ethernet 10G TSN MAC IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Ethernet 10G TSN MAC IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.

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    • Compliant with IEEE Standard 802.3-2018 - Clause 46
    • Supports Preemption as per IEEE Standard 802.1Qbu and IEEE Standard 802.3br Interspersing Express Traffic
    • Supports timing synchronization as per IEEE Standard 1588-2008(PTP) and IEEE Standard 802.1AS(GPTP)
    • Supports Traffic Scheduling - IEEE Standard 802.1Qbv and IEEE Standard 802.1Qav
    • Supports class based flow control and class based FIFO to store each class, total 8 class - IEEE Standard 802.1Q
    • Supports Full duplex mode of operation
    • Ultra low latency and compact implementation
    • Supports MDIO (Clause 22 and Clause 45) Interface
    • Supports Programmable Inter Packed Gap(IPG) and Preamble length
    • Support XGMII (32 bit) interface
    • FCS generation supported
    • Supports VLAN and jumbo frames as an option
    • Independent TX and RX Maximum Transmission Unit (MTU)
    • TSN features can be enabled/disabled independently
    • Cut-through support
    • Configurable Transmit and Receive FIFOs Comprehensive statistics gathering
    • Supports 32bit AXI4 Stream for Packet data
    • In house UNH compliance tested
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    • Scan test ready
    • Simple interface allows easy connection to microprocessor/microcontroller devices
    Deliverables
    • RTL design in Verilog
    • Lint, CDC, Synthesis Scripts with waiver files
    • Lint, CDC, Synthesis Reports
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Technical documentation in greater detail
    • Easy to use Verilog Test Environment with Verilog Testcases

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