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    Ethernet 10G XAUI PCS IP

    OverviewFeaturesRequest Datasheet

    The Ethernet 10G XAUI PCS IP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The Ethernet 10G XAUI PCS IP can be implemented in any technology. The Ethernet 10G XAUI PCS IP core supports Ethernet protocol standard of IEEE 802.3.2018 specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses .The Ethernet 10G XAUI PCS IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Ethernet 10G XAUI PCS IP is validated using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.

      Ethernet-10G-xaui-pcs-silicon-proven-ip-provider-in-china  

    Related Links: Design & Reuse | ChipEstimate | Anysilicon

    • Supports IEEE Standard 802.3.2018 Clause 48 for XAUI PCS
    • Supports 8b/10b encoding on each lane to generate code groups in transmit path
    • Supports 10b/8b decoding on each lane to convert received code groups to 32 XGMII data bits and 4 XGMII control bits
    • Supports synchronization of code groups on each lane to determine code group boundaries
    • Supports deskew of received code-groups from all lanes to an alignment pattern.
    • Supports conversion of XGMII Idle control characters to (from) a randomized sequence of code-groups to enable serial lane synchronization, clock rate compensation and lane-to-lane alignment.
    • Supports Loopback Functionality
    • Support link fault and error indications
    • Supports IEEE Standard 802.3az Energy Efficient Ethernet.
    • Supports Configurable Management Interface (MDIO - Clause 45 / SOC Bus)
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    • Scan test ready
    • Simple interface allows easy connection to Microprocessor/Microcontroller devices
    Deliverables
    • RTL design in Verilog
    • Lint, CDC, Synthesis Scripts with waiver files
    • Lint, CDC, Synthesis Reports
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Technical documentation in greater detail
    • Easy to use Verilog Test Environment with Verilog Testcases

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