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    Ethernet 40G PCS IP

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    Ethernet 40G PCS core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 40G PCS IP is proven in FPGA environment. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.


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    • Supports IEEE Standard 802.3.2018 Clause 82
    • Supports 100GBASE-R
    • Supports 64b/66b encoding and decoding for transmit and receive path
    • Supports data scrambling on the transmit path and descrambling on the receive path
    • Supports Lane Distribution across 20 Lanes for 40Gpbs
    • Supports Block synchronization
    • Supports Alignment Marker insertion and removal
    • Support PCS Lane Deskew and Lane Re-ordering
    • Supports BIP-8 insertion on transmit path and checking on receive path per lane
    • Supports Bit Error Rate monitoring
    • Supports receiver Link fault status detection
    • Supports Loopback functionality
    • Supports for IEEE 802.3az Energy Efficient Ethernet.
    • Supports Configurable Management Interface (MDIO - Clause 45 / SOC Bus)
    • Supports RS FEC as per clause 91 of IEEE Standard 802.3.2018
    • Optional support for Base-R FEC as per clause 74 of IEEE Standard 802.3.2018
    • Programmable PRABS32 and PRABS9 test pattern generators and error checker
    • Configurable Serdes interface
    • Optional support for auto negotiation for backplane Ethernet as per clause 73 of IEEE Standard 802.3.2018
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    • Scan test ready
    • Simple interface allows easy connection to Microprocessor/Microcontroller devices
    • Single Site license option is provided to companies designing in a single site.
    • Multi Sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The Ethernet interface is available in Source and netlist products.
    • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Documentation contains User's Guide and Release notes.

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