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    PCIe4.0 SerDes PHY IP

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    This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE 4.4 interface spec. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since a fore mentioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.

    T2M provides a portfolio of silicon-proven IP for PCI Express consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard for PCI Express, solution which T2M offers is in volume production and has been successfully implemented in a wide range of applications.

      pcie-4-phy-serdes-ip-silicon-proven-ip-core  

    Related Links : Design & Reuse | ChipEstimate | Anysilicon 

       
    • Compliant with PCIe 4.0 Base Specification
    • Compliant with PIPE 4.4
    • Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s
    • Supported physical lane width: x4
    • Supported parallel interface: 32-bit
    • Supported input reference clock: 100 MHz
    • Supported parallel interface data clock: 62.5 MHz, 125 MHz and 250 MHz and 500MHz
    • Supporting low power operation with configurable setting in power state P1/P2/L1
    • PM Substates:
    • PLL control, reference clock control, and embedded power gating control
    • Supports TSMC 12nm FFC 1P9M_2Xa1Xd3Xe2Z_Al=28KA (ULVT/SVT) process
    • Supports TSMC 28nm HPCP 1P9M4X2Y2R (HVT/LVT/EHVT/SVT) process
    • Operating Voltage: 0.8V and 1.2V
    • Providing robust testability by low cost Build-In-Self-Test (BIST) via near-end analog and external loopback interface as well as far-end
    • analog/digital loopback interface
    Benefits
    • Compliant with PCIe® 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Power-gated for lowest leakage in L1.2 low
    • power mode(PMA)
    • Auto power saving for short reach
    • Supported parallel interface: 16/32- bit(Gen4/5), 10/20-bit(Gen1/2/3)
    • PCIe PHY functionality is verified in NCVerilog simulation software using test bench written in Verilog HDL
    Applications
    • SSD Controller
    • Digital TV
    • Setup Box
    • Desktops, workstations, servers
    • Automotive
    • Embedded systems and set-top boxes
    • Network switches and routers
    • Enterprise computing and storage networks
    Deliverables
    • Application Note / User Manual
    • Behavior model, and protected RTL codes
    • Protected Post layout netlist and Standard Delay Format (SDF)
    • Synopsys library (LIB)
    • Frame view (LEF)
    • Metal GDS (GDSII)
    • Test patterns and Test Documentation

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