LIN FlexD Controller IP
- Wireless
- Bluetooth/BLE
- BLE
- Bluetooth
- BT Dual Mode v5.2 RF PHY IP in TSMC 22nm
- BT Dual Mode v5.2 RF PHY IP in GF 22fdx
- BT Dual Mode 5.2 HW Linklayer / BaseBand Controller IP
- BT Dual Mode v5.2 Software Stack & Profiles IP
- BT Dual Mode v5.0 Software Stack & Profiles IP
- Bluetooth MESH v1.1 Software IP
- Bluetooth Dual Mode v4.2 RF Transceiver IP
- Bluetooth Dual Mode SoC White Box IP
- LE Audio
- Cellular
- Audio
- Broadcast
- Lighting
- SerDes
- Controller
- DDR
- PCI Express
- USB
- Controllers
- USB 4.0 Device Controller IP
- USB 4.0 Host Controller IP
- USB 4.0 Hub Controller IP
- USB 3.2 Device Controller IP
- USB 3.2 OTG Controller IP
- USB 3.2 Dual Mode Controller IP
- USB 3.1 Device Controller IP
- USB 3.1 Host Controller IP
- USB 3.1 Hub Controller IP
- USB 3.1 Vision Controller IP
- USB 3.1 Gen1 SSIC Controller IP
- USB 3.0 Device Controller IP
- USB 3.0 Host Controller IP
- USB 3.0 Hub Controller IP
- USB 3.0 Dual Mode Controller IP
- USB 3.0 OTG Controller IP
- USB 3.0 Audio Class Device Controller IP
- USB 2.0 Device Controller IP
- USB 2.0 Host (xHCI) Controller IP
- USB 2.0 Audio Class Device Controller IP
- USB 2.0 OTG Controller IP
- USB 1.1 Device Controller IP
- TSMC 16FF+
- TSMC 22ULP
- TSMC 28HPC+
- TSMC 40LP /LL
- UMC 28HPC+/ HPC
- UMC 40LP
- UMC 55SP /EF
- SMIC 14SF+/ SF++
- SMIC 40LL
- SMIC 55LL
- Controllers
- MIPI
- Controllers
- MIPI UFS v3.1 Device Controller IP
- MIPI UFS v3.1 Host Controller IP
- MIPI UFS v2.1 Host Controller IP
- MIPI CSI-3 Device v1.1 Controller IP
- MIPI CSI-3 Host v1.1 Controller IP
- MIPI CSI-2 Tx v2.0 Controller IP
- MIPI CSI-2 Rx v2.0 Controller IP
- MIPI CSI-2 Rx v1.3 Controller IP
- MIPI CSI-2 Tx v1.3 Controller IP
- MIPI CSI-2 Tx v1.1 Controller IP
- MIPI CSI-2 Rx v1.1 Controller IP
- MIPI DSI2 Tx v1.1 Controller IP
- MIPI DSI2 Rx v1.1 Controller IP
- MIPI DSI Tx v1.2 Controller IP
- MIPI DSI Rx v1.2 Controller IP
- MIPI Unipro v1.8 Controller IP
- MIPI Unipro v1.6 Controller IP
- MIPI I3C Master v1.1 Controller IP
- MIPI I3C Slave v1.1 Controller IP
- MIPI SoundWire Master v1.2 Controller IP
- MIPI SoundWire Slave v1.2 Controller IP
- MIPI RFFE Master Controller IP
- MIPI RFFE Slave Controller IP
- TSMC 12FFC
- TSMC 22ULP
- TSMC 28HPC+
- UMC 28HPC+
- UMC 40LP
- UMC 55 SP
- SMIC 55 LL
- Controllers
- HDMI & DP
- TSMC 12FFC
- TSMC 28HPC+
- HDMI v2.1 Tx-Rx Phy & Controller IP
- HDMI v2.1 Tx PHY & Controller IP
- HDMI v2.1 Rx PHY & Controller IP
- HDMI v2.0 Tx PHY & Controller IP
- HDMI v2.0 Rx PHY & Controller IP
- HDMI-DP Combo Rx PHY IP
- Display Port v1.4 Tx PHY & Controller IP
- Display Port v1.4 Rx PHY & Controller IP
- V-by-One / LVDS Tx IP
- V-by-One / LVDS Rx IP
- TSMC 40LP
- TSMC 65LP / 55LP
- TSMC 65GP / 55GP
- TSMC 90G / 85G
- TSMC 130G / 110G
- UMC 28HPC/HPC+
- UMC 40LP
- UMC 65SP / 55SP
- UMC 110AE
- UMC 130HS
- SMIC 40LL
- SMIC 65LL / 55LL
- SMIC 65G / 55G
- GF 22nm
- GF 28SLP
- GF 65LPe / 55LPe
- Samsung 28FDSOI
- ST 28FDSOI
- STMicro CMOS 40
- IDM 180nm /150nm
- Ethernet
- Video & Graphics
- Analog
- Peripherals
- Services
The DLIN is a soft core of the Local Interconnect Network (LIN). This interface is a serial communication protocol, primarily designed to be used in automotive applications. Compared to the CAN, The LIN is slower, but thanks to its simplicity, it is much more cost effective. Our Core is ideal for communication in intelligent sensors and actuators, where the bandwidth and versatility of the CAN is not required. The DLIN core provides an interface between a microprocessor / microcontroller and LIN bus. It can work as a master or slave LIN node, depending on a work mode determined by the microprocessor / microcontroller. This controller supports transmission speed between 1 and 20kb/s, which allows it to transmit and receive LIN messages compatible to LIN 1.3., LIN 2.1, and the newest 2.2 specification.
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- Conforms with LIN 1.3, LIN 2.1 and LIN 2.2 specification.
- Automatic LIN Header handling
- Automatic Re-synchronization
- Data rate between 1Kbit/s and 20 Kbit/s
- Master and Slave work mode
- Time-out detection
- Extended error detection
- “Break-in-data” support
- Available system interface wrappers:
- AMBA – APB Bus
- Altera Avalon Bus
- Xilinx OPB Bus
- Source code:
- VHDL Source Code or/and
- VERILOG Source Code or/and
- Encrypted, or plain text EDIF
- VHDL & VERILOG test bench environment
- Active-HDL automatic simulation macros
- ModelSim automatic simulation macros
- Tests with reference responses
- Technical documentation
- Installation notes
- HDL core specification
- Datasheet
- Synthesis scripts
- Example application
- Technical support
- Automotive
- Industrial
- Embedded communication systems