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    XPHY Low power Chip to Chip SerDes IP

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    These IPs are targeted at applications requiring high speed, high bandwidth, low-power consumption, and low-latency interfaces.

    t2m-design-reuse t2m-chipestimate t2m-anysilicon
    • Low Power Chip-to-Chip SERDES
    • From 10Gb/s to 11Gb/s
    • Technology: 28FDSOI 8ML & 10ML
    • Platform: 1 Data Slice and 1 Clock Slices
    • RX: AC or DC coupling with low-power CTLE
    • TX: Power-optimized resistive bridge driver
    • Optimized for Low Power Chip-to-Chip SERDES Applications
    • Ultra low voltage operation
    • Optimized for low power Chip to Chip SERDES Applications
    • IOT
    • Wearables

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