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T2M MIPI MIPI D-PHY Tx IP in GF 55LP

MIPI D-PHY Tx IP in GF 55LP

Description and Features

The D-PHY specification, version 1.2, is completely complied with by the MIPI D-PHY Analog TX IP Core. The Display Serial Interface and the MIPI Camera Serial Interface (CSI-2) are both compatible with it (DSI protocols). One clock lane and four data lanes make up this TX PHY. An analogue front end produces and receives electrical level signals, while a digital back end controls the I/O operations. automatic calibration for an inbuilt termination resistor A MIPI DSI PHY (MIPI TX DPHY), the D-PHY consists of a PLL, a Clock Lane, four Data Lanes, and a clock lane in addition to a D-PHY that may be used as a GPIO bank with a 5V tolerance.

 

Features
  • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2

  • Supports standard PPI interface compliant to MIPI Specification

  • Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s

  • Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s

  • Supports ultra-low power mode, high-speed mode and escape mode

  • Supports one clock lane and up to four data lanes

  • Data lanes support transfer of data in high-speed mode

  • Supports error detection mechanism for sequence errors and contentions

  • Supports contention detection

  • Configurable skew option for each Clock and Data lanes

  • Testability for TX, RX and PLL

  • Silicon Proven in GF 55LP.

Deliverables

  • GDSII & layer map

  • Place-Route views (.LEF)

  • Liberty library (.lib)

  • Verilog behaviour model

  • Netlist & SDF timing

  • Layout guidelines, application notes

  • LVS/DRC verification reports