Version 1.2 of the D-PHY specification is completely complied with by the MIPI D-PHY Analog TX IP Core. It is compatible with the Display Serial Interface and the MIPI Camera Serial Interface (CSI-2) (DSI protocols). With one clock lane and four data lanes, it is a Tx PHY. A digital back end controls the I/O operations, and an analogue front end produces and receives electrical level signals. auto-calibrating internal termination resistor The D-PHY is a MIPI DSI PHY (MIPI TX DPHY) and has a PLL, a clock lane, four data lanes, and a clock lane. It can be used as a GPIO bank with a 5V tolerance.
Compliant to MIPI Alliance Standard for
D-PHY specification Version 1.2
Supports standard PPI interface compliant to MIPI Specification
Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
Supports ultra-low power mode, high-speed mode and escape mode
Supports one clock lane and up to four data lanes
Data lanes support transfer of data in high-speed mode
Supports error detection mechanism for sequence errors and contentions
Supports contention detection
Configurable skew option for each Clock and Data lanes
Testability for TX, RX and PLL
Silicon Proven in UMC 55 LP.
Deliverables
GDSII & layer map
Place-Route views (.LEF)
Liberty library (.lib)
Verilog behaviour model
Netlist & SDF timing
Layout guidelines, application notes
LVS/DRC verification reports
