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T2M PCI Express PCIe 3.0 SerDes PHY IP

PCIe 3.0 SerDes PHY IP

Description and Features

This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 interface spec. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.

T2M offers best in class highly configurable PCIe 3.0 PHY, targeted for both enterprise and client application, complaint to PCie 3.0 specification and ECN 1.0a. The PHY IP is designed to support a wide range of applications and can provides maximum throughput through its eight lanes configuration. The customer has a choice to customize it for lower data rates (Gen2) or lower number of lanes. It also supports L1 sub states L1.1 and L1.2 which enables its seamless integration in power constraint applications, while keeping low in the silicon area.

T2M offers an option of complete integrated PCIe 3.0 hard IP including controller as a complete system solution.


  • Compliant with PCIe 3.0 Base Specification
  • Compliant with PIPE 4.3
  • Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
  • Supports PCIe 3.1, 2.1, 1.1 encoding, backchannel initialization
  • Provide robust testability by low cost Build-In-Self-Test (BIST) and near/far end loopback at analog/digital interface
  • Silicon Proven in TSMC 28HPC+UMC 28HPC+UMC 40LPUMC 55SPSMIC 14SF+ /SF++ Process
  • Supporting low power operation with configurable setting in power state
  • hysical coding sublayer (PCS) block with PIPE interface
  • Supports PCIe 3.1, 2.1, 1.1 encoding, backchannel initialization
  • Spread-spectrum clocking (SRIS)
  • Supports PCIe power management features, including L1 substate; power gating and power island; DFE bypass option and voltage mode Tx with under drive supply options
  • Multi-channel PHY macro with single clock and control core for higher density
  • Supports both internal and external reference clock inputs
  • PC (Desktops, Laptops)
  • Storage Area Networks (SAN)
  • Solid State Drives (SSD)
  • Networking Interface card
  • Server
  • Setup Box
  • Digital TV
  • Mobile
  • Repeater
  • Behavior model, and protected RTL codes
  • Protected Post layout netlist and
  • Standard Delay Format (SDF)
  • Synopsys library (LIB)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation