This Peripheral Component Interconnect Express (PCIe) x4 PHY IP supports PCIe3.1 transmission. This is compliant with PCIe Rev3 Base Specification with support of PIPE 4.3 interface spec. Input clock frequency as 25Mhz, the output data rate(serial) supports all three 2.5 Gbps, 5.0 Gbps, 8.0 Gbps. 10 Pads is required and the max clock speed is 500MHz.
Operating Voltage Range : - 0.99V-1.21V, typical=1.1V - 2.97V-3.63V,typical=3.3V
The PHY is Silicon Proven and in Production in various applications.
Support PHY interface (PIPE4.3) enables multiple IP sources for USB3 MAC layer
Supports 5.0Gbps and 10Gbps serial data transmission rate Supports 16-bit or 32-bit parallel interface Data and clock recovery from serial stream
Support 8b/10b encoder/decoder(5Gbps), 128/130 encoder/decoder(BGbps) and error indication
Tunable receiver detection to detect worse case cables
Beacon transmission and reception
Support SSCG function to reduce EMI effects with tunable down-spread amplitude
Selectable TX margining, TX de-emphasis and signal swing values
Built-in-self-test with internal Loopback test option
Programmable analog circuit parameter adjustment and internal test control