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T2M Peripherals eSPI Master / Slave Controller IP

eSPI Master / Slave Controller IP

Description and Features

eSPI controller is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of standard eSPI specification. Through its eSPI compatibility, it provides a simple interface to a wide range of low-cost devices. ESPI controller IP is proven in FPGA environment. The host interface of the eSPI controller can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol. eSPI Controller IP is supported natively in Verilog and VHDL.



  • Compliant with eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.0.
  • Supports Master and Slave Modes
  • Supports Single, Dual and Quad modes
  • Supports TX and RX operation as per specs
  • Supports below transaction phases • Command Phase • Turn-Around Phase • Response Phase
  • Supports baud rate selection
  • Supports Slave triggered transaction
  • Supports Power management Event
  • Supports Interrupts and Alert
  • Supports In-band reset
  • Supports below multiple channels • Peripheral Channel • Virtual Wires Channel • OOB Message (Tunnelled SMBus) Channel • Run-time Flash Access Channel
  • Various kind of Master and Slave errors detection and handling
  • Supports CRC checking
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices


  • The eSPI CONTROLLER interface is available in Source and netlist products.
  • The Source product is delivered in Verilog. If needed, VHDL and SystemC can also be provided
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.