Production Proven, Complex Semiconductor IP Cores

IP Cores

T2M SerDes JESD204B Tx-Rx PHY IP


Description and Features

JESD204B interface provides full support for the JESD204B synchronous serial interface, compatible with JESD204B.01 version specification. Through itscompatibility, it provides a simple interface to a wide range of low-cost devices. JESD204B PHY IP is proven in SMIC 12nm, SMIC 14nm, TSMC 28nm, TSMC 55nm, UMC 28nm and UMC 55nm.




  • Multiple lanes transceiver with data rate from 1Gbps to 15Gbps:Transceiver version including both receiver and transmitter • Transmitter only version
  • 40bit/32bit/20bit/16bit selectable parallel data bus Independent per-lane power down control
  • Programmable transmit amplitude
  • Programmable 3-tap feed forward equalizer(FFE)
  • Embedded receiver equalization (CTLE and DFE) to compensate insertion loss
  • Build in self-test with multiple pattern generation and checker for production test
  • Flexible reference clock frequency range
  • Integrated LC-tank PLL and Ring OSC PLL
  • Integrated on-chip differential 100-ohm termination for reference clock
  • Low capacitance ESD structures
  • Integrated on-chip differential 100 ohm termination in TX and RX : Termination resistance auto calibration function (optional)
  • Support both Flip Chip Package and Wire Bonding Package
  • Testability: High Testability • Built-in pattern generator and checker including PRBS Internal serial loopback
  • Reliability: Life Time : 10 years • Life Time Average Temperature : up to 110 degC (include hot-spot) • Availability : 100% • ESD (HBM) : over 2000V • ESD (CDM) : over 250V • Latch-up : Satisfy JESD78 ClassII (Tj=125c), >100mA


  • Application Note / User Manual
  • Behavior model, and protected RTL codes
  • Protected Post layout netlist and Standard
  • Delay Format (SDF)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation