Description and Features
JESD204B interface provides full support for the JESD204B synchronous serial interface, compatible with JESD204B.01 version specification. Through itscompatibility, it provides a simple interface to a wide range of low-cost devices. JESD204B PHY IP is proven in SMIC 12nm, SMIC 14nm, TSMC 28nm, TSMC 55nm, UMC 28nm and UMC 55nm.
Features
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Multiple lanes transceiver with data rate from 1Gbps to 15Gbps:Transceiver version including both receiver and transmitter • Transmitter only version
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40bit/32bit/20bit/16bit selectable parallel data bus Independent per-lane power down control
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Programmable transmit amplitude
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Programmable 3-tap feed forward equalizer(FFE)
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Embedded receiver equalization (CTLE and DFE) to compensate insertion loss
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Build in self-test with multiple pattern generation and checker for production test
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Flexible reference clock frequency range
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Integrated LC-tank PLL and Ring OSC PLL
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Integrated on-chip differential 100-ohm termination for reference clock
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Low capacitance ESD structures
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Integrated on-chip differential 100 ohm termination in TX and RX : Termination resistance auto calibration function (optional)
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Support both Flip Chip Package and Wire Bonding Package
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Testability: High Testability • Built-in pattern generator and checker including PRBS Internal serial loopback
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Reliability: Life Time : 10 years • Life Time Average Temperature : up to 110 degC (include hot-spot) • Availability : 100% • ESD (HBM) : over 2000V • ESD (CDM) : over 250V • Latch-up : Satisfy JESD78 ClassII (Tj=125c), >100mA
Deliverables
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Application Note / User Manual
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Behavior model, and protected RTL codes
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Protected Post layout netlist and Standard
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Delay Format (SDF)
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Frame view (LEF)
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Metal GDS (GDSII)
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Test patterns and Test Documentation