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    H.264 Encoder IP

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    The H.264 Encoder IP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The H.264 Encoder IP can be implemented in any technology. The H.264 Encoder core supports the ISO/IEC 14496-10/ITU-T H.264 specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses. The H.264 Encoder IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The H.264 Encoder IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation

      H-264-Encoder-silicon-proven-ip-provider-in-europe   Related Links: Design & Reuse | ChipEstimate | Anysilicon
    • Supports ISO/IEC 14496-10/ITU-T H.264 specification.
    • Supports full H.264/AVC Encoder functionality.
    • Supports video resolution up to 3840x2160@60fps.
    • Supports all type of prediction methods. • Inter prediction • Intra prediction
    • Supports profile level up to 6.2.
    • Supports precision 8 bits and 10 bits.
    • Supports AAC and AC-3 audio Encoder.
    • Supports all Chroma type 4:4:4, 4:2:2 and 4:2:0.
    • Supports following in VBR encoding mode • Rate-Distortion optimized output. • Output up to 240 MBits/s
    • Supports following in CBR encoding mode • On-the-fly rate changes. • Output up to 240 MBits/s
    • Output Annex B NAL byte stream
    • Supports optional advanced thresholding of quantized transform coefficients.
    • Supports run-time tunable operation enables decoder compatibility trade-offs
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    • Scan test ready
    • Simple interface allows easy connection to microprocessor/microcontroller devices
    • RTL design in Verilog.
    • Lint, CDC synthesis script with waiver files.
    • Lint, CDC synthesis reports.
    • IP-XACT RDL generated address map.
    • Firmware code and Linux driver package.
    • Technical documentation in greater detail.
    • Easy to use Verilog test environment with Verilog test cases.
    • Fully compliant, silicon-proven core.
    • Comes with Verilog testbench and option to buy full advanced System Verilog Testbench
    • Support directly from engineer who designed the code.
    • Based on RMM (Re Use Methodology Manual guidelines).
    • Supports all the Synthesis tools.

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