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    MPEG2 Encoder IP

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    MPEG2 Encoder core is compliant with MPEG-2 standard specification. Through its compatibility, it provides a simple interface to a wide range of lowcost devices. MPEG2 Encoder is proven in FPGA environment. The host interface of the MPEG2 can be simple interface or can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.


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    • Supports MPEG-2 standard specification.
    • Supports full MPEG-2 encoder functionality.
    • Supports video resolution up to 1920x1080@60fps.
    • Supports input bit rates up to 100Mbps.
    • Supports all type of prediction methods. • Inter prediction • Intra prediction
    • Supports Chroma type 4:2:2 and 4:2:0.
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    • Scan test ready
    • Simple interface allows easy connection to Microprocessor/Microcontroller devices
    • Single site license option is provided to companies designing in a single site.
    • Multi sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The MPEG2 Encoder interface is available in Source and netlist products.
    • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Documentation contains User's Guide and Release notes.

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