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Blitter Graphics and Display IP

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Blitter display - 2D graphic and display Hardware accelerator with SW control for customization. It is fully Compliance with standard graphic libraries and buffer formats (DirectFB, Android HWComposer)

Graphics blitter - Multi task and scalable, high performance, 2D graphic accelerator, SW control, Standard graphics software library acceleration (DirectFB, Wayland/Weston, Android Hardware composer). It has very low latency, QoS, Security & Virtualization support, Memory Bandwidth optimization.

Ensures Source and destination windows all defined using an XY descriptor, with pixel accuracy whatever the format, from 1bpp to 32bpp.

Most of these operators can be combined in a single BDisp pass.The BDisp works from memory to memory with a triple, dual or single source and one target.


  • Solid color fill of rectangular window & Solid color shade (fill + alpha blending)
  • Gradient fill of rectangular window (horizontal and Vertical gradient)
  • Color expansion (CLUT to true color) & correction (gamma, contrast, gain)
  • Rectangular clipping & Color Keying capability
  • 1-bit/8-bit clip mask bitmap for random shape clipping can be achieved in two passes
  • Plane mask feature available, Spatial De-Interlacing
  • Bi-endianness support, 90 degrees and multiples rotation support
  • 4:2:2 / 4:2:0 capabilities, as source format (2 buffer split format : field or frame Macro Block or Raster)
  • YUV capabilities, as source format (3 buffer split format)
  • 2D resize engine with high quality filtering, Horizontal and Vertical
  • VC1 “Range mapping / Range reduction” compensation algorithm
  • Fully programmable Matrix used for color space conversion, PSI, special effect
  • Programmable source/target scanning direction, both horizontally and vertically, in order to cope correctly with overlapping source and destination area
  • Adaptive Flicker filter from memory to memory (Shared between S1 and S2)
  • One source copy, with one or several operators enabled (color format conversion, 2Dscaling)
  • Two-source copy with alpha blending or logical operation between them
  • Deliverables

  • Verilog Source RTL Code plus Simulation Environment
  • C Source Code
  • Physical Design scripts - Synopsys synthesis
  • Hardware simulation test bench with regression test suit
  • Reference platform drivers
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