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    68000 IP

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    Description

    The D68000 soft core is binary-compatible with the industry standard 68000 32-bit microcoprocessor. It has a 16-bit data bus and a 24-bit address data bus. Of course, its code is compatible with the MC68008, upward code compatible with MC68010 virtual extensions and the MC68020 32-bit implementation of the architecture. Our efficient IP Core has an improved instructions set, which allows to execute the program with higher performance, than a standard 68000 core.

    The D68000 is delivered with fully automated test-bench and complete set of tests, which allow easy package validation at each stage of SoC design flow.

    A special testing platform has been built to run D68000 with uCLinux Operating System

    68000-ip

    Performance

    Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below

    1385216237_68000-size

    Features

    • Software compatible with 68000 industry standard
    • MULS, MULU take 28 clock periods
    • DIVS, DIVU take 28 clock periods
    • Optimized shifts and rotations
    • Idle cycles removed to improve performance
    • Shorter effective address calculation time
    • Bus cycle timings identical to 68000
    • 32 bit data and address registers
    • 14 addressing modes:
      • Direct:
        • Data register direct
        • Address register direct
      • Indirect:
        • Register indirect
        • Postincrement register indirect
        • Predecrement register indirect
        • Register indirect with offset
        • Indexed register indirect with offset
      • PC relative:
        • Relative with offset
        • Relative with index and offset
      • Absolute data:
        • Absolute short
        • Absolute long
      • Immediate data:
        • Immediate
        • Quick immediate
        • Implied
    • 5 data types supported:
      • bits
      • BCD
      • bytes, words and long words
    • Arithmetic Logic Unit includes:
      • 8,16,32-bit arithmetic & logical operations
      • 16x16 bit signed and unsigned multiplication
      • 32/16 bit signed and unsigned division
      • Boolean operations
    • Interrupt controller:
      • 7 priority levels interrupt controller
      • Unlimited number of virtual interrupt sources
      • Vectored and auto-vectored modes
    • Memory interface includes:
      • Up to 4 GB of address space
      • 16-bit data bus
      • Asynchronous bus control
    • M6800 family synchronous interface
      • 3- and 2- wire bus arbitration
      • Supervisor and user modes
    • Fully synthesizable
    • Static synchronous design
    • Deliverables

    • Source code:
      • VHDL Source Code or/and 
      • VERILOG Source Code or/and 
      • Encrypted, or plain text EDIF 
    • VHDL & VERILOG test bench environment 
      • Active-HDL automatic simulation macros 
      • ModelSim automatic simulation macros 
      • Tests with reference responses 
    • Technical documentation 
      • Installation notes 
      • HDL core specification 
      • Datasheet 
    • Synthesis scripts 
    • Example application 
    • Technical support 
      • IP Core implementation support 
      • 3 months maintenance 
      • Delivery the IP Core updates, minor and major versions changes 
      • Delivery the documentation updates 
      • Phone & email support 

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