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    6811E IP

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    Description

    The DF6811 is an advanced 8-bit MCU IP Core, with highly sophisticated, on-chip peripheral capabilities. DF6811 soft core is binary-compatible with the industry standard Motorola 68HC11 8-bit microcontroller. It has an improved FAST architecture, that is approximately 4 times faster, compared to original implementation. In the standard configuration, the core has integrated on chip, major peripheral functions.
    The Core can be provided in configurations, that match the following:
    • 68HC11F/K
    • 68HC08/05/11E/11F/K
    • MC6803/02/09/03/02
    An asynchronous serial communications interface (SCI) and separate synchronous serial peripheral interface (SPI), are included. The main 16-bit, free-running timer system has three input capture and five outputcompare lines and a real-time interrupt function.
    An 8-bit pulse accumulator subsystem can count external events or measure external periods. Self-monitoring on-chip circuitry is included, to protect DF6811E from system errors. A computer operating properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non maskable interrupt if illegal opcode is detected.
    Two software-controlled power-saving modes - WAIT and STOP are available, to conserve additional power. These modes make the DF6811E IP Core especially attractive for automotive and battery-driven applications. The DF6811E has a built-in real time hardware on-chip debugger -DoCDTM, allowing easy software debugging and easy package validation at each stage of SoC design flow.
    14695970196811f
     

    Features

    • FAST architecture, 4 times faster than the original implementation
    • Software compatible with industry standard 68HC11
    • 10 times faster multiplication
    • 16 times faster division
    • De-multiplexed Address/Data Bus to allow easy integration with external memories.
    • Interrupt Controller
    • Two power saving modes: STOP, WAIT
    • Fully synthesizable, static synchronous design with no internal tri-states
    • No internal reset generator or gated clock
    • Scan test ready

    Deliverables

    • Source code:
    • VHDL Source Code or/and
    • VERILOG Source Code or/and
    • Encrypted, or plain text EDIF
    • VHDL & VERILOG test bench environment
    • Active-HDL automatic simulation macros
    • ModelSim automatic simulation macros
    • Tests with reference responses
    • Technical documentation
    • Installation notes
    • HDL core specification
    • Datasheet
    • Synthesis scripts
    • Example application
    • Technical support

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