SoC White Box IPs

Channel bandwidth:

• • Up to 5.4bps per channel (HBR2

Programmable analog characteristics:

• • CDR Bandwidth
  • Equalizer strength
  • Terminator resistor
  • BGR voltage

Testability:

• • PLL only test
  • Analog signal monitor

Process:

• • TSMC28 1.8v/0.9v

Features

• • eDP version 1.4a compliant receiver
  • Consists of two main link channels and one AUX channel Supports 1.62Gbps (RBR) to 5.4Gbps (HBR2) bit rate
  • Supports main link operation with 1 or 2 lanes
  • Integrated 100-ohm termination resistors with common-mode biasing
  • Integrated equalizer with tunable strength
  • Configurable analog characteristics
  • CDR bandwidth
  • Equalizer strength
  • Terminator resistance
  • BGR voltage
  • Regulator voltage
  • Support PLL test and internal analog signal monitor
  • 1.8V/0.9V power supply
  • Support TSMC 28nm process

Deliverables:

• • Verilog RTL or netlist source code of LINK controller.
  • Abstracted timing models for synthesis and STA
  • Timing constrains for synthesis and physical layout
  • Behavioral Verilog Model, simulation test bench, run control scripts, and test stimuli
  • Physical design database
  • Integration guidelines
  • Reference software sample code