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    8051 IP

    OverviewFeaturesRequest Datasheet


    The DQ8051CPU is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller, designed to operate with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management unit PMU. The DQ8051CPU soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. The DQ8051CPU has a built-in configurable DoCD-JTAG on chip debugger, supporting Keil µVision development platform and standalone DoCD debug software. Dhrystone 2.1 benchmark program runs from 19.69 to 26.62 times faster than the original 80C51 at the same frequency. This performance can also be exploited to great advantage in low power applications, where the core can be clocked over ten times more slowly than the original implementation, with no performance penalty. The DQ8051CPU is fully customizable - it is delivered in the exact configuration to meet your requirements. There is no need to pay extra for not used features and wasted silicon.
    The DQ8051CPU is delivered with fully automated testbench and complete set of tests, allowing easy package validation at each stage of SoC design flow.
    Each of DCD's 8051 cores has a built-in support for DCD's Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
    Unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of the microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. More details about DCD's on-chip debugger


    • software is 100% compatible with 8051 industry standard
    • Quad-Pipelined architecture enables to run 26.62 times faster, than the original 80C51 at the same frequency
    • Up to 25.053 VAX MIPS at 100 MHz
    • 24 times faster multiplication
    • 12 times faster division
    • 2 Data Pointers (DPTR) - for faster memory blocks copying
      • Advanced INC & DEC modes
      • Auto-switch of current DPTR
    • Up to 256 bytes of internal (on-chip) Data Memory - IDM
    • Up to 64k bytes of Program Memory
    • Up to 16 MB of external (off-chip) Data Memory - XDM
      • Synchronous interface - for up to 64K bytes of (on-chip) fast external Data Memory - (SXDM)
    • User programmable Program Memory Wait States solution -  for wide range of memories' speed
    • User programmable External Data Memory Wait States solution - for wide range of memories' speed
    • De-multiplexed Address/Data bus - to allow easy memory connection
    • Interface for additional Special Function Registers
    • Fully synthesizable
    • Static synchronous design
    • No internal tri-states
    • Scan test ready


    • DQ8051CPU core area and performance in ASIC devices -results given for working system with two DPTRs and connected 256B IDM, 8kB CODE and 2kB SXDM memories. All CPU features and Peripherals have been included. DoCD JTAG debugger increases core size by approximately 2 100 gates.
    • DQ8051CPU core area and performance in XILINX devices -results given for working system   with two DPTRs and connected 256B IDM, 8kB CODE and 2kB SXDM memories. All CPU features and Peripherals have been included.
    • DQ8051CPU core area and performance in ALTERA devices -results given for working system   with two DPTRs and connected 256B IDM, 8kB CODE and 2kB SXDM memories. All CPU features and Peripherals have been included.


    Source code:

    • VHDL Source Code or/and
    • VERILOG Source Code or/and
    • Encrypted, or plain text EDIF
    • VHDL & VERILOG test bench environment
    • Active-HDL automatic simulation macros 
    • ModelSim automatic simulation macros 
    • Tests with reference responses 
    • Technical documentation 
    • Installation notes 
    • HDL core specification 
    • Datasheet 
    • Synthesis scripts 
    • Example application 
    • Technical support 
    • IP Core implementation support 
    • 3 months maintenance 
    • Delivery the IP Core updates, minor and major versions changes 
    • Delivery the documentation updates 
    • Phone & email support 

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