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    DVB T2/T Modulator IP

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    The CMS0009 DVB-T/DVB-H Modulator provides all the necessary processing steps to modulate a single (or pair of hierarchical) transport stream(s) into a complex I/Q signal for input to a pair of DACs, or an interpolating DAC device such as the AD9857 or AD9957. Optionally the output can be selected as an IF to supply a single DAC.

    The design has been optimized to provide excellent performance in low cost FPGA devices such as the Cyclone range from Altera or the Spartan range from Xilinx

    Processing Steps are Following:
    • Randomiser
    • Reed-Solomon Encoder
    • Outer Interleaver
    • Convolutional Encoder
    • Interleaver
    • QAM Mapper
    • Framer
    • In-band equalization
    • IFFT
    • Resampler
    • Baseband-to-IF
    • DAC Aperture Correction
    • Radio Interface
    • Register Bank


    • Fully compliant with ETSI EN 300 744 V1.5.1. Extension core available for DVB-T(H) support.
    • Enables rapid development of audio/visual systems using commodity Free-to-Air set-top-box technology and low-cost FPGAs.
    • Configurable support for 2K and 8K OFDM modes and hierarchical transmission. (4k for DVB-T(H)).
    • Variable channel bandwidth support using a single.
    • clock reference; 5MHz… 8MHz.
    • AD9857/AD9957/AD9789 interface and auto- programming support.
    • AD9516/ADF4350 PLL programming support.
    • Optional dual-core combining into the AD9857 for multi-channel applications.
    • Extension core available for SPI/ASI interface with integrated PCR TS re-stamping, NULL TS packet removal/filtering, NULL/PRBS TS packet insertion, input and output TS rate estimation registers.
    • Seamless integration with Altera ASI megacore when using SPI/ASI extension core.
    • Optional FFT output windowing. Optional critical-mask output filtering.
    • Optional in-band or output pre-distortion. Optional noise interference source.
    • Modes that are not required may be removed with synthesis options to generate a compact, efficient design.
    • Designed for very efficient FPGA implementation without compromise to the targeting of gate array or standard cell structures.
    • Supplied as a protected bitstream or netlist (Megacore for Altera FPGA targets).

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