SoC White Box IPs

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    HDMI V1.4 Rx Link Controller IP

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    Description

    HDMI receiver Link IP core which is fully compliant with HDMI 1.4a specification. This offers a simple implementation for system on chip (SOC) for consumer electronics like HD-TV, AV receiver. Its performs most efficiently with HMDI receiver PHY IP core. This HDMI core functions can be customized based on requirements.

    Features

    • HDMI version 1.4a, HDCP revision 1.3 and DVI version 1.0 compliant receiver
    • Supports DTV from 480i to 1080i/p HD resolution, and PC from VGA to UXGA
    • Supports 3D video format specified in HDMI 1.4a specification
    • Programmable 2-way color space converter
    • Compliant with EIA/CEA-861D
    • Deep color supported up to 16bit per pixel.
    • xvYCC Enhanced Colorimetry
    • All packet reception including Gamut Metadata Packet
    • Supports RGB, YCbCr digital video output format including ITU.656
    • 24/30/36/48bit RGB/YCbCr 4:4:4
    • 16/20/24bit YCbCr 4:2:2
    • 8/10/12bit YCbCr 4:2:2 (ITU.601 and 656)
    • 48 bit mode is not supported in 1080p
    • Supports standard SPDIF output for stereo or compressed audio up to 192KHz
    • Support PCM, Dolby digital, DTS digital audio output through 4bits I2S up to 8 channel
    • IEC60958 or IEC61937 compatible
    • 1bit audio format (Super Audio CD) output
    • High-bitrate compressed audio formats output
    • Slave I2C interface for DDC connection
    • Configuration registers programmable via synchronized parallel interface
    • Interface to external HDCP key storage

    Deliverables

    • Configurable RTL Code
    • HDL based test bench and behavioral models
    • Test cases
    • Protocol checkers, bus watchers and performance monitors
    • Configurable synthesis shell
    • Documentation
    • Design Guide
    • Verification Guide
    • Synthesis Guide

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