SoC White Box IPs

Schedule a meeting

HDMI v1.4b Receiver IP

OverviewFeaturesRequest Datasheet


The HDMI Receiver IP provides an integrated functionality to interface with an HDMI compliant source and extract the corresponding video and audio signals. HDMI RX IP design provides a solution for organizing receiving data from link in accordance with DVI/HDMI1.1/HDMI1.2/HDMI1.3/HDMI1.4 with 3D interfaces and HDCP 1.4. IP is composed of HDMI v1.4 core and Physical Layer, in 65nmLP and 28nmLP.
Video: Full support for CEA 861 & HDMI 1.4b
Audio: All formats including Compressed, HBR & 1 bit audio
Data: Reception of standard
Supports Combo PHY (Display Port or HDMI) that de-serializes up to 3 gbps input. Maximum output speed is 240 MHz
Supports TMDS PHY (HDMI only input) that de-serializes up to 2.25 gbps input. Maximum output speed is 562.5 MHz
Link rate from 25MHz to 165MHz (DVI/HDMI1.1), up to 225MHz for HDMI1.3/1.3a and up to 297MHz for HDMI1.4
Option of 1:1, 2:1, 3:1 and 4:1 Mux
Cable equalizer and integrated line impedance matching per channel
Supports 3D video timing up to 1080P 60fr/Eye
RGB/YUV444/YUV422 color spaces; xv YCC support All possible color depth as HDMI 1.4
Automatic video/audio type detection and mute generation for excepted conditions
Up/Down color depth dithering at the video output
Automatic video screen blocking by programmed background color during video mute
Internal image format measurement block


  • 4x I2S output for up to 8-channel PCM at 192 KHz or 61937-compressed stream
  • Configurable Output interface to SoC
  • Parallel video bus 24/30/36/48bit pixels, I2S audio out and 32 bit parallel audio output format, 1bit transmitter
  • Host CPU interface using STBus-T1 – Optional I2C, PBUS
  • I2C slaves for HDCP and DDC2Bi
  • Option on
  • o CEC 1.4 transceiver and message-level decode
  • o I2C Slave for MCCS with multiplexer to/from Any EDID channels
  • o Internal EDID I2C slave
  • External and internal EDID support on all ports
  • Crypto Core and NVS interface
  • Deliverables

  • Datasheet
  • Integration guideline
  • GDSII or Phantom GDSII
  • Layer map table
  • CDL netlist for LVS
  • LEF
  • Verilog behavior model
  • Liberty timing model
  • DRC/LVS/ERC results
Fill the form below, to receive the product datasheet in your inbox