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    14b-4.32Gsps ADC IP

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    This ultra high speed wide-band Analog-to-Digital Converter is based on 16 Time Interleaved Pipeline sub-ADC followed by a digital correction algorithm for gain, offset and skew correction. The differential input is terminated by a 100 Ohms resistor (100 Ohms differential) and followed by an input buffer driving the sub-ADC. The signal amplitude is 1Vpp differential. The analog source driving the ADC should be ac-coupled to the input pins with two external capacitors of 1nF minimum. The input common mode is generated internally.



      • 14-bit Time-Interleaved Pipeline ADC
      • 4.32GSps Sampling Rate
      • 60dBFS SNR (9.7 ENOB) with 54MHz<Fin<1794MHz
      • External AC coupling for the input signal
      • Two power supplies: 1.8V for analog & 1.0V for digital compensation
      • 1.0Vpp differential full-scale input
      • Buffered analog inputs
      • Input signal bandwidth: 54MHz to 1794MHz
      • Power down mode
      • 16x14bits data output at 270 MHz (4.32GHz/16)
      • Data ready output at 270MHz
      • Silicon Proven : 28FDSOI
      • Extracted from a production DOCSIS Tuner STB chip


      • Source Code Delivery including : Unlimited Usage and Rights to Modify
      • Technical documents
      • Design Guide

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