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    MIPI CSI 3 Host Controller IP

    OverviewFeaturesRequest Datasheet

    The MIPI Camera Serial Interface 3 (CSI-3) is an interface between a Camera and a host processor baseband application engine. This interface, defined by MIPI Alliance, uses Unipro and MPHY for Link and PHY layers respectively. CSI-3 Host is the command encoding and pixel decoding logic between the Application processor and UniPro. The CSI-3 Host IP supports two C-Ports for pixel data and one C-Port for attribute transfer. In the CSI-3 Host, the pixel data from UniPro, along-with CDP data is processed at C-port level, and subsequently the image is processed before being sent to the Application Processor. The control flow, being opposite to data flow, is initiated by the application processor, to configure UniPro, and MPHYs downstream in both Host and Device sides, and also CSI-3 Device. The MIPI CSI-3 Host along with our MIPI UniPro, MPHY and our MIPI CSI-3 Device provide a complete solution for a camera application.


      • Compliant with MIPI CSI-3 Spec v1.0
      • 1 C-port for CPC and 2 C-ports for Pixel/Embedded Data
      • CPC GET/SET/Notify/Response PDU Supported.
      • Mandatory Gettable/settable properties of all attributes.
      • End-to-end Support for CPC Packets.
      • Round Robin arbitration for multiple VCIDs.
      • Tx Buffer Overflow Management
      • Preemptive frame handling
      • Embedded data during Vertical Blanking period supported
      • 2 source pixel data interleaving


      • FPGA Validation
      • Highly Modular and Scalable Design
      • Active Low Asynchronous Reset


      • RTL Code
      • Verification Environments
      • Test suites
      • Synthesis Environment and Scripts
      • Design Guide
      • Verification Guide
      • Synthesis Guide

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