SoC White Box IPs

Schedule a meeting


OverviewFeaturesRequest Datasheet


T2M offers best in class highly configurable PCIe 3.0 PHY, targeted for both enterprise and client application, complaint to PCie 3.0 specification and ECN 1.0a. The PHY IP is designed to support a wide range of applications and can provides maximum throughput through its eight lanes configuration. The customer has a choice to customize it for lower data rates (Gen2) or lower number of lanes. It also supports L1 sub states L1.1 and L1.2 which enables its seamless integration in power constraint applications, while keeping low in the silicon area.
T2M offers an option of complete integrated PCIe 3.0 hard IP including partner company controller and standalone PHY IP.
  • Available PCI PHY
  • PCIe 3.0 8 & 16Gbps
  • Foundry - 65,55,28nm


  • PCIe 3.0 PHY with backward compatibility
  • Supports L0-L2 power states and L1.1 and L1.2 substates
  • Configurable parallel data width 8,16,32 Bits, OCTAL ( 8Tx, 8Rx) QUAD ( 4 TX and 4RX ), Single Lane Configuration (1 Tx, 1Rx)
  • Support Signal loss & receiver detection with CTLE and 3 Tap DFE receiver equalization
  • Support upto 20 inch SL channel
  • Optimized Metal Stakes for Lower NRE expense ( 6020+LB )
  • 1.0V supply to support -40 to 125 Deg.C
  • CDR logic for better data alignment and locking , Integrated PCS Layer; compliant to PIPE specification
  • Applications

  • Storage Area Networks (SAN)
  • Solid State Drives (SSD)
  • Networking Interface card
  • Server
  • Repeater
  • Deliverables

  • White Box Design Data Base
  • GDSII ported to required process node
  • Physical Design scripts - Synopsys synthesis
  • Datasheet, Characterization Report
  • Comprehensive documentation and Support
Fill the form below, to receive the product datasheet in your inbox