SoC White Box IPs

    Schedule a meeting

    PCIe 3.0 SerDes PHY IP

    OverviewFeaturesRequest Datasheet
    (日本語)

    This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 interface spec. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.

    T2M offers best in class highly configurable PCIe 3.0 PHY, targeted for both enterprise and client application, complaint to PCie 3.0 specification and ECN 1.0a. The PHY IP is designed to support a wide range of applications and can provides maximum throughput through its eight lanes configuration. The customer has a choice to customize it for lower data rates (Gen2) or lower number of lanes. It also supports L1 sub states L1.1 and L1.2 which enables its seamless integration in power constraint applications, while keeping low in the silicon area. T2M offers an option of complete integrated PCIe 3.0 hard IP including controller as a complete system solution.

      pcie-3-phy-serdes-ip-silicon-proven-ip-core    

    Related Links: Design & Reuse | ChipEstimate | Anysilicon 

       
    (日本語)
    • Compliant with PCIe 3.0 Base Specification
    • Compliant with PIPE 4.3
    • Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
    • Provide robust testability by low cost Build-In-Self-Test (BIST) and near/far end loopback at analog/digital interface
    • Silicon Proven in UMC 28HPC+ Process
    • Supporting low power operation with configurable setting in power state
    Benefits
    • PCIe PHY functionality is verified in NCVerilog simulation software using test
    • bench written in Verilog HDL
    • Per lane real-time, non-destructive internal
    • eye measurement
    • Multiple internal test patterns, including PRBS
    • and 256-bit user-defined pattern
    • Supports forward/reverse analog and digital loopbacks
    Applications
    • Storage Area Networks (SAN)
    • Solid State Drives (SSD)
    • Networking Interface card
    • Server
    • Setup Box
    • Digital TV
    • Mobile
    • Repeater
    Deliverables
    • Behavior model, and protected RTL codes
    • Protected Post layout netlist and
    • Standard Delay Format (SDF)
    • Synopsys library (LIB)
    • Frame view (LEF)
    • Metal GDS (GDSII)
    • Test patterns and Test Documentation

      Fill the form below, to receive the product datasheet in your inbox