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USB 3.0 Hub controller IP

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The USB 3.0 Hub controller is a highly configurable core and implements the USB 3.0 Hub functionality that can be interfaced with third party USB 3.0 PHY's. The Hub Controller core can be configured to support up to 15 downstream ports and the core supports all USB 3.0 defined power states. The design is carefully partitioned to support standard power management schemes. Optionally, it can be configured to manage power mode transitions of the controller and the USB 3.0 PHY for aggressive power savings required for bus powered hubs.

The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and most importantly, the target technology. GDA solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications.


  • Compliant with USB3.0 Specification Version 1.0
  • Configurable number of downstream ports
  • Configurable Core Frequency
  • Configurable Internal datapath width: 32, 64, or 128 bits
  • Compliant with standard USB 3.0 PHY Interface
  • Configurable PHY Interface width: 8, 16, or 32 bits
  • Efficient buffering scheme for forwarding packets through hub with minimal latency
  • Supports Bus and Self Powered Hub implementations
  • USB 3.0 low power states support
  • Support for various Hardware and Software Configurability regarding Core characteristics
  • Register Interface for internal Register Access
  • Support of Hardware and Software Configurability
  • Configurable Buffer sizes
  • Configurable shared buffers or per port buffers
  • Configurable number of Downstream Ports
  • Benefits

  • Highly modular and configurable design
  • Layered architecture
  • Fully synchronous design
  • Supports both sync and async reset
  • Clearly demarked clock domains
  • Software control for key features
  • Master and slave loop backs for debug
  • Aggressive power management
  • Deliverables

  • Design RTL Code
  • Verification Environment
  • Tests suites
  • Synthesis Environments & scripts
  • Design Guide
  • Verification Guide
  • Synthesis Guide
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