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USB3.0 PHY IP

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The USB3.0 PHY IP is a complete physical layer (PHY) IP solution designed for mobile and consumer applications. Compliant with the USB3.0 base specifications, the PHY IP integrates mixed-signal circuits to support both 2.5GT/s and 5.0GT/s data transmission rates. The USB3.0 PHY IP consists of both the Physical Media Attachment (PMA) layer and the Physical Coding Sublayer (PCS), and connects easily to either the USB MAC layer using the standard PIPE-3.0 interface.

The USB3.0 PHY IP transceiver is optimized for low power consumption and minimal die area (sub-0.30mm2), without sacrificing performance and high-data throughput. The USB3.0 PHY IP comprises a complete on-chip physical transceiver solution with Electro Static Discharge (ESD) protection, built-in self test module with embedded jitter injection, and a dynamic equalization circuit that ensures full support for high-performance designs.

 
  • Compliant with USB3.0 base specification
  • Standard PHY interface (PIPE) enables multiple IP sources for USB3 MAC layer
  • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
  • Supports 16-bit or 32-bit parallel interface
  • 8b/10b encoder/decoder and error indication
  • Tunable Receiver detection to detect worse case cables
  • Low Frequency Periodic Signaling (LFPS) transmission and reception in USB3.0 mode
  • Supports SSC to reduce EMI effects with tunable down-spread amplitude
  • Selectable TX margining, Tx de-emphasis and signal swing values
  • Internal Loopback Test Capable
  • Allowable analog circuit parameter adjustment and internal test control
  • Built-in Self Test with embedded Jitter Injection
  • Output Jitter reduction with constant power technique
  Applications
  • PC, Television
  • Data storage
  • Multimedia Devices
  • Recorders
  • Mobile device
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