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USB3.0 Host Controller

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The USB3.0 host controller is a highly integrated and cost-effective IP. It contains a USB3.0 PHY and a USB2.0 PHY. The USB3.0 PHY is used for Super-Speed (SS) transfers and the USB2.0 PHY is used for High-Speed (HS), Full-Speed (FS), and Low-Speed (LS) transfers.


  • One USB3.0 downstream port
  • Compliant with XHCI Specification, Revision 1.0
  • Compliant with USB 2.0 Specification, Revision 2.0
  • Compliant with USB 3.0 Specification, Revision 1.0
  • Supports DFT test for digital parts of the controller
  • Supports Loopback test for USB2.0 PHY and USB3.0 PHY
  • USB2.0 PHY:
  • Compliant with USB 2.0 specification, Revision 2.0
  • Supports High-Speed (480Mbps), Full-Speed (12Mbps) and Low-Speed (1.5Mbps) serial data rates
  • Embedded 45ohm High-Speed termination, 1.5kohm Full-Speed device pull-up resistor, 15kohm pull-down resistors
  • Embedded Phase-Locked Loop (PLL) for 480MHz High-Speed USB operations
  • Embedded internal RREF for reference current trimming function
  • Embedded HV protection circuit
  • USB3.0 PHY:
  • Compliant with USB 3.0 specification, Revision 1.0
  • Provides one 5Gbps Super-Speed connection
  • 270MHz differential CMOS reference clock
  • 0.9V/1.8V supply rails
  • On-chip 50Ω termination resistors
  • 10-bit parallel interface (@ 500MHz)
  • Programmable transmitter output swing and de-emphasis strength
  • Configurable/adaptive equalizer to optimize receiver sensitivity
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