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    MIPI Unipro v1.8 Controller IP

    OverviewFeaturesRequest Datasheet

    This MIPI UniPro Controller IP is compliant with the latest MIPI UniPro v1.8 specification, provides the capability to control the UniPro link over a MIPI M-PHY link. MIPI UniPro is a high-performance, chip-to-chip, serial interconnect bus for mobile applications.

    When this MIPI UniPro Controller IP is combined with Universal Flash Storage (UFS) Controller IP and also our M-PHY IP, designers can easily integrate PHY and the controller with low risk and accelerate time-to market with our UFS IP solution.

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    • Compliant with the MIPI UniPro v1.8 specification and backward compatible with MIPI UniPro v1.61
    • Support HS-Gear4 M-PHY IP v4.1 and access to attribute
    • Support Asymmetric lanes and Gears
    • Support Data Lanes connected 2 lanes
    • Support Slow/ Slow-Auto/ Fast/ Fast-Auto mode
    • Support PWMG1-G4/HSG1-G4/Rate A/B
    • Support Skip symbol insertion
    • Support Scramble function
    • Support Quality of Service Monitoring (QoS)
    • Support PHY test mode & UniPro test feature
    • Support Cport0 and TC0
    • Support HW auto LinkStartUp
    • Maximum R/W Performance up to 2170MB/s
    • UniPro IP Power-Off in Hibernate state
    • User Manual
    • Behavior model
    • RTL codes
    • Test patterns
    • Test Documentation
    • Highly Modular and scalable design
    • Active-low
    • Asynchronous reset
    • IOT
    • Automotive
    • Storage
    • Consumer
    • Embedded
    • Enterprise

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