MIPI I3C Master v1.1 Controller IP

Description

I3C interface is a fast, low cost, low power, two wire digital interface for sensors in mobile wireless products, compliant with MIPI Alliance. Our I3C supports several communication formats all sharing a two wire interface - SDA and SCL. SDA is a bidirectional data pin while SCL can be either a clock pin or a data pin while in HDR mode. The type of communication supported by I3C. I2C-like communication with SCL clock speed up to 12.5 MHz , MIPI-defined transmissions that allow the master to communicate to one or all slaves on the bus.

HDR mode using ternary number symbols to achieve two data transmissions per equivalent clock cycle. A subset of I2C communication to legacy I2C slaves, if present on the bus. Slave initiated request to master, e.g. In-band interrupt, address request.

Features

• Compliant with the MIPI Alliance Draft Specification for I3C Version 0.5 Revision 1.0
• Supports all modes of Master – SDR [12.5 MHz], HDR and HDR-DDR, I2C Modes.
• Supports interrupt handling.
• Enables peer to peer communication.
• Detects hot Join of slave devices.
• Dynamic Addressing support.
• Support In-Band Interrupt
• Automatic retry configurability for failure slave transactions.
• Error check and reporting of master and slave errors.
• Highly configurable and gate efficient core.
• Compliant with AMBA 3 APB Protocol Specification v1.0 for register access.
• Easy integration and co-existence with I3C devices.
• Supports Legacy I2C mode
• Can be configured to work as secondary master
• Dynamic addressing assignment capability
• Support for slave generated in-band interrupts
• Memory for retaining bus device addresses

Deliverables

• Configurable RTL Code
• HDL based test bench and behavioral models
• Test cases
• Protocol checkers, bus watchers and performance monitors
• Configurable synthesis shell
• Documentation
• Design Guide
• Verification Guide
• Synthesis Guide